PCI-Express Interface Design and Implementation for ARM Cortex CPU

2019 COE Engineering Design Project (GK04)

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Faculty Lab Coordinator

Gul Khan

Topic Category

FPGA / Reconfigurable Computing

Preamble

Peripheral Component Interconnect Express (PCIe or PCI-E) is a serial expansion bus standard for connecting a computer/CPU to one or more high performance peripherals and other devices such as accelerators, GPUs, etc. Expansion of an existing ARM-CPU based FPGA board to include some sophisticated hardware functionality required for a computational platform is an interesting project. The expansion can be in terms of an I/O controller to connect storage, network interface or accelerator. PCI-E interface will constitute a complete design project. The capstone design group is to choose a basic version of the PCI-e protocol for implementation, and design it by using Verilog or VHDL to complete an RTL IP of PCIe controller. The design can be tested and verified using System-Verilog from the module to the System level. The HDL design is to be prototyped on the FPGA and demonstrate through basic communication with a PCI-e based system.

Objective

HDL or RTL (Verilog or VHDL) design and implementation of PCI-express bus protocol for ARM Cortex CPU accommodated over an FPGA board.

Partial Specifications

1. Study the basic PCI-E interface and its protocol for FPGA implementation.
2. Select one of the PCI-E protocols from PCI Express 2 or 3 for RTL (HDL) implementation.
3. Use Verilog or VHDL for hardware implementation of the protocol.
4. Synthesis of the selected PCI-E HDL design of the protocol and implement it for the target FPGA board.
5. Identify a PCI-E based device or board to be interfaced with your PCI-E design.
6. Verify the newly designed PCI-E by interfacing it to a PCI-E based system.

Suggested Approach

1. Investigate various I/O protocols including SATA and PCI express and understand basics of PCI-E protocol for implementation.
2. Study and select various FPGA platforms for PCI-E implementation.
3. Study Verilog/VHDL for RTL (HDL) design of PCI-E I/O protocol.
4. Design and Implement the HDL of the protocol.
5. Synthesize your HDL design of the protocol and implement it on the FPGA platform.
6. Interface a PCIe based system via the implemented protocol.

Group Responsibilities

1. Study various types of PCI express protocols including PCI Express 2 or 3.
2. Select either the PCI express protocol for design and implementation.
3. Study various FPGA platforms for PCI-E implementation and select a target FPGA board/platform. The FPGA board may also have an ARM Cortex CPU.
4. Study Verilog or VHDL for HDL (hardware) design of the selected PCI-E protocol.
5. Design and Implement (preferably Verilog-based) the RTL of the protocol.
6. Synthesize the HDL design of the protocol and implement it on the FPGA platform.
7. For verification, interface a PCI-E based system via the implemented protocol with the FPGA board.

Student A Responsibilities

1. Investigate various I/O protocols (including SATA and PCI express) for implementation.
2. Study a couple of suitable FPGA-based platform (having an ARM Cortex CPU) for the PCI-E protocol implementation.
3. Study Verilog or VHDL for HDL design of the selected PCI express (2 or 3) protocol.
4. Develop part-1 of the RTL hardware design of PCI-E using Verilog or VHDL.
5. Develop and synthesize the PCI-E protocol (RTL) design by working with Student B and C for the target FPGA platform.
6. Assist Student B, C and D and manage the overall project design and implementation.

Student B Responsibilities

1. Study various PCI-E (1, 2 and 3) protocols for design and FPGA implementation.
2. Study suitable FPGA-based platforms (having an ARM Cortex CPU) and identify one for PCI-E protocol implementation.
3. Study Verilog or VHDL for HDL design of the selected PCI express (2 or 3) protocol.
4. Develop part-2 of the RTL hardware design of PCI-E using Verilog or VHDL.
5. Develop and synthesize the PCI-E protocol (RTL) design by working with Student A and C for the target FPGA platform.
6. Assist Student A, C and D and manage the overall project design and implementation.

Student C Responsibilities

1. Study various PCI-E (1, 2 and 3) protocols for design and FPGA implementation.
2. Identify a suitable FPGA-based platforms (having an ARM Cortex CPU) for PCI-E protocol implementation.
3. Study Verilog or VHDL for HDL design of the selected PCI express (2 or 3) protocol.
4. Develop part-3 of the RTL hardware design of PCI-E using Verilog or VHDL.
5. Develop and synthesize the PCI-E protocol (RTL) design by working with Student A and B for the target FPGA platform.
6. Assist Student A, B and D and manage the overall project design and implementation.

Student D Responsibilities

1. Investigate some candidate FPGA boards and/or platforms for PCI-E implementation.
2. Study the selected PCI express protocol for implementation.
3. Study Verilog or VHDL for RTL (hardware) design of the selected PCI express protocol.
4. Participate in the RTL design of the protocol using Verilog or VHDL.
5. For verification, interface a PCIe based system via the implemented protocol with the FPGA board.
6. Assist Student A, B and D to manage the overall project and implementation.

Course Co-requisites

COE718, COE838