G. Khan
Same as FLC
uP/Instrumentation, Networking, Software
An FPGA device that can accommodate multiple CPU cores, memory and a vast
range of peripherals. For example, Altera supports Nios-II embedded processor
cores and Avalon bus that provides a set of pre-defined signals with which
a user can connect one or more IP blocks including CPU cores, DMA controller,
UART, memory controller and other peripherals. A dedicated multi-core Network-on-Chip
(NoC) can be easily developed and prototyped by putting it on a single FPGA
(e.g. Stratix or Cyclone from Altera) for various high performance multimedia
applications. One of the main component of NoC is a router which is attached
to a processing core (CPU or hardware accelerator) and tranfer messages from
one NoC processing core to another core.
To investigate, design and develop a multiple CPU and other hardware cores
based embedded SoPC for multimedia applications. The multimedia applications
ranging from MPEG-2, JPEG2000 to complex systems can be implemented on an
NoC system.
1. Investigate and study NoC systems.
2. Investigate and study routing techniques for NoC systems
3. Investigate and select a multimedia application suitable for multi-core
NoC
implementation.
4. Study of the suitability of Nios-II processor or Pico/Micro Blaze based
SoPC
platform.
5. Specify and partition the Multimedia application for NoC multi-core
implementation.
6. Design and implement a router suitable for NoC architecture.
7. Design and develop the Multicore NoC system for the application and implement
a Multicore system.
1. Investigate and study Nios-II processor architecture and programming
model, specifically interrupt mechanism and other characteristics to support
multi-core NoC implementation. Investigate the capabilities of Nios-II processor
and memory cores
2. Investigate and study some candidate multimedia applications.
3. Study Altera Stratix/Cyclone FPGA based embedded platform to be employed
for multimedia devices.
4. Investigate and study the results of research and development being conducted
by various multi-core implementations of the multimedia application.
5. Select the multimedia application and develop a detailed multi-core specification
of the application.
6. Partition the multimedia application suitable for multi-core implementation.
7. Implement a routing technique suitable for NoC systems.
8. Design and implement a router for the NoC.
7. Design, implement and prototype a NoC system for the application using
the Nios-based SoPC.
1. Investigate and study Nios-II processor architecture and programming
model.
2. Study Stratix/Cyclone FPGA based embedded platform for multimedia applications.
3. Investigate the results of research and development being conducted by
various research groups working on Multicore/SoC based Multimedia applications.
4. Develop a detailed specification of Multicore/NoC implementation of the
Multimedia application.
5. Design, develop, implement and prototype the NoC system for the application.
1. Study some candidate SoPC-based embedded platform.
2. Investigate and study the capabilities of CPU and Memory Cores.
3. Choose a multimedia application suitable for multi-core implementation.
4. Design and write the Multimedia application specification in a high level
language e.g. C or SystemC.
5. Assist Student A and C and manage the overall project design and implementation.
1. Study the suitability of NoC and SoPC for Multimedia Applications
2. Study some multi-core embedded platform developed for multimedia applications.
3. Partition the multimedia application for multi-core implementation working
with Student A.
4. Design NoC router architecture and establish communication between routers.
5. Design and establish communication between a source core and the router.
6. Design and establish communication between a router and the destination
core.
7. Assist Student A and C to manage the overall project design and implementation.
1. Study the suitability of SoPC for Multimedia Embedded Applications.
2. Investigate some candidate Nios processor-based embedded platforms.
3. Use the specification (developed by student A) and partitioning information
(developed by student B)
4. Design, develop and implement an embedded computer hardware architecture
using the specification and consisting of Nios-II CPU, Avalon Bus, memory
and peripheral IPs from Altera by using Quartus and SoPC builder tools.
5. Overall design of NoC and mapping of application to NoC developed.
6. Assist Student A and B to manage the overall project design and implementation.
COE718
Mon Sep 4 14:37:51 EDT 2017