A Smart Home Gate Reminder

FLC Name

G. Khan

FA Name

G. Khan

Topic Category

uP/Instrumentation

Preamble

System on Programmable Chips (SoPCs) has been widely used to implement embedded computer systems. Altera-Nios embedded processor core supported by an Avalon bus provides a set of pre-defined signals with which a user can connect one or more IP blocks including DMA controller, UART, memory controller and other peripherals. A dedicated embedded computer system for gate reminder in a smart-home can be easily prototyped by putting it in a single FPGA.

Gate Reminder is a family shared embedded computer system located at the front door area that can display informative messages, reminding users of things they need to take and know before leaving home. We already have a number of reminders in our daily life including alarm clock, a scheduler in a PDA, etc. In a smart home, the household appliances, utilities, entertainment centers, thermostats, and other devices should be able to communicate with the gate reminder.

Objective

To investigate, design and develop a SoPC based gate reminder embedded computer system for smart homes.

Partial Specifications

Investigate the user requirements of a Gate reminder.
Study of a suitable real-time operating system to implement gate reminder using
a Nios processor based platform from Altera.
The environment must support a priority based multiple task scheduling.
Design and develop the gate reminder embedded computer hardware and application
software.

Suggested Approach

Develop a detailed hardware-software specification of gate-reminder.
Investigate and study Nios (or u-Blaze) processor architecture and programming model, specifically interrupt mechanism and other characteristics to support multitasking. Study some candidate real-time operating systems for Nios or u-Blaze processor-based embedded platform.
Study Stratix or Cyclone FPGA based embedded platforms to be employed for gate-reminder implementation.
Implement and prototype a gate-reminder embedded computer system using a Nios (or u-Blaze) based embedded platform.

Group Responsibilities

Design and develop a SoPC based prototype of a gate reminder embedded computer system for smart homes.
The implementation includes embedded hardware and software systems.
 

Student A Responsibilities

Study Altera Stratix or Xilinx Vertex FPGA based SoPC embedded platforms to be employed for gate-reminder application.
Develop a detailed specification of gate reminder
Design, develop, implement and prototype a gate-reminder embedded system
Manage the overall project design and implementation

Student B Responsibilities

Investigate some candidate real-time operating systems for Nios or u-Blaze processor-based embedded platforms.
Design, develop and write the gate-reminder application code in a multitasking environment
Assist Student A to manage the overall project design and implementation

Student C Responsibilities

Investigate the suitability of SoPC for Embedded applications like gate-reminder
Study some candidate Nios processor-based embedded platforms.
Design, develop and implement an embedded computer hardware architecture for gate-reminder embedded system, which consists of Nios CPU and peripheral IPs from Altera by using Quartus and SoPC builder development tools.
Assist Student A to manage the overall project design and implementation

Course Pre-requisites

COE538, COE618 and COE718