Two Dimensional Complementary Clock Linear Feedback Shift Register (LFSR)

This Project is involved to a test-per-scan BIST with a new structure of 2-D LFSR named 2-D Complementary Clock LFSR (2-D CCLFSR) as the pseudorandom pattern generator and an MISR as the response analyzer, which has been designed and implemented in the E1/E2 circuit. The circuit is divided into 9 parallel scan paths. A parity check circuit as the space compactor is used to decrease the entire test time. The E1/E2 multiplexer is designed in VHDL at RTL level including the BIST architecture. Layout generation follows the synthesis of the VHDL code. The test structure of the circuit, the 2-D CCLFSR (and MISR), is designed to allow changes to its size by altering the parameters. The location of feedback lines and input inverters and selecting clocks for flip-flops in the 2-D CCLFSR can also be designed by modifying the parameters, lead to 20% reduction in hardware overhead. The layout of the E1/E2 multiplexer with BIST structure is designed using Alliance Layout Generator. In order to test the BIST structure of the circuit, physical faults were generated in the layout. Fault coverage of 97% was achieved.

Built-In Self-Test is one of the most important methods for testing integrated circuits, in which we can use on-chip circuitry to generate test patterns and analyze the responses of the circuit. There are in general two types of BIST: test-per-clock and test-per-scan. In test-per-clock BIST, applying one test vector and capturing its response, accomplishes in each clock cycle. test-per-scan BIST, uses a serial scan path or multiple scan paths to shift in test patterns and shift out the responses at the same time. Pseudorandom testing applies a certain length of test patterns with randomness properties. Various techniques enhance the quality of pseudorandom testing especially for detecting random pattern resistant faults. Some of these techniques apply a series of pre-computed test vectors (deterministic patterns) in addition to pseudorandom patterns, to detect random pattern resistant faults. One of the new structures is using two dimensional Linear Feedback Shift Register(2-D LFSR) or configurable 2-D LFSR [1,2] as the pattern generator for generating deterministic patterns and then pseudorandom patterns with low hardware overhead.

In this paper a kind of 2-D LFSR called 2-D Complementary Clock LFSR (2-D CCLFSR) is introduced that uses a two-phase clock and adds additional choices for constructing a 2-D LFSR to generate the required deterministic patterns and gives additional options to the optimization software resulting in a less hardware overhead than before. The proposed 2-D CCLFSR has been used in a test-per-scan architecture in E1/E2 multiplexer circuit and shows a less hardware overhead than conventional 2-D LFSR, but like 2-D LFSR it can be used in test-per-clock systems as well.