| Instructor(s) | Dr. Gul Khan [Coordinator] Office: ENG448 Phone: (416) 979-5000 x 556084 Email: gnkhan@torontomu.ca Office Hours: 12:00-1:00PM Wednesday | ||||||||||||||
| Calendar Description | This course will cover the basics of system-on-chip (SoC) design, hardware-software co- specification, co-synthesis and network-on-chip (NoC) systems. It provides the advance knowledge required for system-on-chip design, multi-core architectures and embedded systems on a chip. Students will also be introduced to the main principles of SoC modeling and design using SystemC. Various soft processor cores such as Nios-II and other IPs will be explored. Interconnection structures such as AMBA, Avalon and IBM Core-connect for SoC design will be covered in detail. Various SoC development tools will be utilized in the labs and projects. | ||||||||||||||
| Prerequisites | COE 718 or ELE 734 | ||||||||||||||
| Antirequisites | None | ||||||||||||||
| Corerequisites | None | ||||||||||||||
| Compulsory Text(s): |
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| Reference Text(s): |
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| Learning Objectives (Indicators) | At the end of this course, the successful student will be able to:
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB). | ||||||||||||||
| Course Organization | 3.0 hours of lecture per week for 13 weeks | ||||||||||||||
| Teaching Assistants | Mr. Yoga Suhas Kuruba Manjunath, yoga.kuruba@torontomu.ca | ||||||||||||||
| Course Evaluation |
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable). | ||||||||||||||
| Examinations | Midterm Exam in Week 6, 65-80 minutes. Final Exam, during exam period, 2 hours. | ||||||||||||||
| Other Evaluation Information | None | ||||||||||||||
| Other Information | None | ||||||||||||||
Week | Hours | Chapters / | Topic, description |
|---|---|---|---|
1 | 3 | Introduction to System on Chip (SoC) | |
2 | 3 | Introduction to SystemC, SoC Co-specification | |
3 | 3 | SystemC based Modeling and Analysis of SoCs | |
4 | 3 | Hardware-Software Cosynthesis and Accelerators based Embedded System Design | |
5 | 3 | Basics of Chips and SoC ICs | |
6 | 3 | Midterm Exam | |
7 | 3 | SoC-Platforms and DE1-SoC Design Methods for SoC Project and Labs | |
8 | 3 | NoC (Network on Chip) and NoC based Interconnection. | |
9 | 3 | NoC based Interconnection: Regular (Mesh, Torus, Tree, etc.) and Application Specific NoC Topologies. | |
10 | 3 | On-Chip Interconnection: On-Chip Busses including AMBA, Core-connect, Avalon, etc. | |
11 | 3 | Soft CPU Cores: ARM-A9, OpenRISC, Leon4, OpenSPARC, etc. | |
12 | 3 | SoC Verification and UVM | |
13 | 3 | SoC Application Case Studies (If time permits) |
Week | L/T/A | Description |
|---|---|---|
2 | ENG412 | Lab1: SystemC: Introduction and Tutorial. |
3 | ENG412 | Lab 2a: SystemC based Accelerator for SoC. |
4 | ENG412 | Lab 2b: JPEG Encoder/Decoder SoC Design using SystemC. |
5 | ENG412 | Lab2a and Lab2b Demo and Submission |
6 | ENG412 | Introduction to Course Project |
7 | ENG412 | Lab4: Designing and Interfacing Custom IP with an FPGA/HPS System. |
8 | ENG412 | Lab4 Completion and Demo |
9 | ENG412 | Project Progress |
10 | ENG412 | Project Progress and Interim Report |
11 | ENG412 | Project Progress |
12 | ENG412 | Project Demo and Completion |
13 | ENG412 | Project Presentation and Final Report |
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Refer to the Departmental FAQ page for furhter information on common questions.
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