Andy Gean
Ye received his Ph.D. degree in Computer
Engineering from the University of Toronto
in 2004. He also received his B.A.Sc. and M.A.Sc. degrees
from the same university in 1996 and 1999, respectively. In 1996, he graduated
first in class in the Engineering
Science program; and from 1999 to 2000, he participated in the development of
the Ultragizmo
board for the University of Toronto Undergraduate Microprocessor
Laboratory.
·
EE8506: Digital CMOS VLSI Integrated Circuits
·
ELE734 Low-Power
Digital Integrated Circuits
·
COE538
Microprocessor Systems (2005-2010)
·
ELE202 Electric
Circuits Analysis (2006-2011, 2014)
·
FPGA
Architectures: Datapath-Oriented FPGAs and FPGA Architectures Targeting
Biomedical Applications.
·
Applications
of FPGAs for Implementing Advanced Biomedical Signal Processing Algorithms.
·
Applications
of FPGAs for Implementing Advanced Computer Graphics and Digital Video
Processing Algorithms.
·
VLSI
System Modeling and Performance Evaluation.
·
Digital
Signal Processing and Digital Video Processing Algorithms and their VLSI
Implementation.
My research group currently has positions open for graduate studies at the
M.A.Sc. and Ph.D. levels. We seek capable and hardworking
individuals who are interested in further developing digital hardware
design skills at the RTL level for FPGA/ASIC systems and/or C/C++
programming skills in developing CAD tools for digital hardware optimization.
The candidate should have a B.A.Sc./M.A.Sc. degree in Computer Engineering
or Computer Science.
·
Field-Programmable
Gate Array (FPGA) architectures
·
Computer-Aided
Design (CAD) tools for FPGAs
·
Logic
synthesis
·
Hardware
implementation of digital communication algorithms
·
Hardware
implementation of computer graphics algorithms
·
Very
Large Scale Integrated (VLSI) circuit design
·
CAD
tools for VLSI circuit design
·
Computer
architecture
·
Anas Razzaq (Ph.D.)
·
Sajjad Rostami-Sani (Ph.D.)
·
Mousa Al-Qawasmi (Ph.D.)
·
Mousa Al-Qawasmi
(M.A.Sc. – Thesis): Ph.D. Candidate at Toronto Metropolitan University (Ryerson)
·
Farheen Fatima Khan (Ph.D. – Thesis): AMD
·
Julien Li Chee Ming (Post Doctoral Research): Autonmous Technologies
·
Nafiul Hyder
(M.A.Sc. – Thesis): AMD Markham
·
Muhammad Umair Zafar
(M.A.Sc. – Thesis): AMD Markham
·
Alaa R. Abdullah
(Ph.D. – Thesis): Australian College of Kuwait
·
Omesh
Mutukuda (M.A.Sc. – Thesis): AMD Markham
·
Jasmina Vasiljevic (M.A.Sc.
– Thesis): Ph.D. Candidate at University of Toronto
·
Shahin
Lotfabadi (M.A.Sc. – Thesis): Intelligent Automation Inc.
·
Hamid Asefi (M.A.Sc. – Thesis)
·
Sebastian
Ip (M.A.Sc. – Thesis): Altera Toronto
·
Phoebe
Ping Chen (M.A.Sc. – Thesis): AMD Markham
·
Theepan Moorthy (M.A.Sc. – Thesis):
Ph.D. Candidate at University of
British Columbia
·
M.Eng.: Jian Ming Yu,
Shivendra Jairam Lee,
Sang-Joon Lee,
Alexis Mabini,
Ganendran Narasingavel,
Walid El-Mestrah,
Chen Bin Dai,
Dilshad Bhatti
·
Sajjad Rostami Sani and Andy Ye,
“Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of
Switch Blocks for Tile-Based FPGAs in FinFET 7nm,”
ACM Transactions on Reconfigurable Technology and Systems,
doi.acm.org?doi=3639055. [PDF]
·
Anas Razzaq, Sajjad Rostami-Sani, and Andy Ye,
“The Effect of Gate Voltage Boosting on the Power Efficiency of Multi-Context FPGAs,”
Elsevier Integration, the VLSI Journal,
Vol. 86, No. 9,
September 2022,
pp. 30-43. [PDF]
·
Sajjad Rostami-Sani and Andy Ye,
“Measuring the Effect of Track Count and Wire Segment Length on the Layout Area of Switch Blocks for Tile-Based FPGAs,”
Elsevier Microprocessors and Microsystems,
Vol 92, No. 7,
July 2022.
[PDF]
·
Sajjad Rostami-Sani, Anas Razzaq, and Andy Ye,
“Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm,”
Proceedings of the 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines,
New York City, NY,
May 2022,
pp 1-9. (Acceptance Rate: 17.5%) [PDF]
·
Anas Razzaq, Sajjad Rostami-Sani, and Andy Ye,
“Designing Efficient FPGA Tiles for Power-Constrained Ultra-Low-Power Applications,”
Elsevier Integration, the VLSI Journal,
Vol. 78, No. 5,
May 2021,
pp. 124-134. [PDF]
·
Anas Razzaq and Andy Ye,
“Static Power Model for CMOS and FPGA Circuits,”
IET Computers & Digital Techniques,
Vol. 15, No. 4,
April 2021,
pp. 263-278. [PDF]
·
Sajjad Rostami-Sani, Farheen Khan, and Andy Ye,
“Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology,”
Proceedings of the 2020 IEEE 30th International Conference on FieldProgrammable Logic and Applications,
Gothenburg, Sweden,
August 2020,
pp. 214-219. (Acceptance Rate: 32%) [PDF]
·
Farheen Khan and Andy Ye, “An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures,” ACM Transactions on Reconfigurable Technology and Systems, Vol. 11, No. 1, March 2018. [PDF]
·
Farheen Khan and Andy Ye, “A Study on the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area,” Elsvier Microprocessors and Microsystems, Vol. 52, No. 7, July 2017, pp. 287-298. [PDF]
·
Farheen Khan and Andy Ye, “An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures,” Proceedings of the 2016 26th International Conference on Field Programmable Logic and Applications, Lausanne, Switzerland, September 2016, pp. 1-11. (Best Paper Award, Acceptance Rate: 21%) [PDF]
·
Farheen Khan and Andy Ye, “Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area,” Proceedings of the 2015 23rd IEEE International Syposium on Field-Programmable Custom Computing Machines, Vancouver, British Columbia, May 2015, pp. 223-226. (Short Paper, Acceptance Rate: 38.9% Long and Short Paper Combined) [PDF]
·
Fei Yuan, Alaa R. Abdullah and Andy Ye, “Design Techniques for Decision Feedback Equalisation of Multi-giga-bit-per-second Serial Data Links: a State-of-the-art Review,” IET Circuits, Devices and Systems, Vol. 8, No. 2, April 2014, pp. 118-130. [PDF]
·
Alaa R. Abdullah, Fei Yuan and Andy Ye, “New 2-D Eye-Opening Monitor for Gb/s Serial Links,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 6, June 2014, pp. 1209-1218. [PDF]
·
Jasmina Vasiljevic and Andy
Ye, “Analysis and Architecture Design of Scalable Fractional Motion Estimation
for H.264 Encoding,” Elsevier Integration, the VLSI
Journal, Vol. 45, No. 4, April 2012, pp. 427-438. [PDF]
·
Shahin
Sanayei Lotfabadi, Andy Ye, Sridhar Krishnan,
“Measuring the Power Efficiency of Subthreshold FPGAs
for Implementing Portable Biomedical Applications,” Elsevier Microprocessors
and Microsystems – Embedded Hardware Design, Vol. 36, No. 3, March 2012, pp.
151-158. [PDF]
·
Jasmina
Vasiljevic and Andy Ye,
“The Effect of Scaling on the Area and Performance of the H.264/AVC Full-Search Fractional MOtion Estimation Algorithm on FPGAs,” IET Computers and Digital Techniques, Vol. 6, No. 2, February 2012, pp. 95-104. [PDF]
·
Omesh
Mutukuda, Andy Ye, Gul Khan, “Utilizing Multi-Bit
Connections to Improve the Area Efficiency of Unidirectional Routing Resources
for Routing Multi-Bit Signals on FPGAs,” Elsevier Microprocessors and
Microsystems – Embedded Hardware Design, Vol. 36, No. 3, March 2012, pp.
167–175. [PDF]
·
J.
Luu, I. Kuon, P. Jamieson,
T. Campbell, A. Ye, W. Fang, K. Kent, and J. Rose,
“VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver
Routing, Heterogeneity and Process Scaling,” ACM Transactions on Reconfigurable
Technology and Systems, Vol. 4, No. 4, December 2011, pp. 32–54. [PDF]
·
Ping
Chen and Andy Ye, "The Effect of Multi-Bit Correlation on the Design of
Field-Programmable Gate Array Routing Resources," IEEE Transactions on
Very Large Scale Integration Systems, Vol. 19, No. 2, February 2011, pp.
283-294. [PDF]
·
O.
Mutukuda, A. Ye, and G. Khan, “The Effect of
Multi-bit Based Connections on the Area Efficiency of FPGAs Utilizing
Unidirectional Routing Resources,” Proceedings of the 2010 IEEE International
Conference on Field-Programmable Technology, Tsinghua
University, Beijing, China, December 2010, pp. 216–223. [PDF]
·
Andy
Ye, "Using the Minimum Set of Input Combinations to Minimize the Area of
Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os
in FPGAs," IEEE Transactions on Very Large Scale Integration Systems, Vol.
18, No. 1, January 2010, pp. 95-107. [PDF]
·
Jason
Luu, Ian Kuon, Peter
Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, and Jonathan Rose, "VPR
5.0: FPGA CAD and Architecture Exploration with Single-Driver Routing,
Heterogeneity and Process Scaling," Proceedings of the 2009 ACM/SIGDA 17th
International Symposium on Field-Programmable Gate Arrays, Monterey,
California, February 2009, pp. 133-142. [PDF]
·
Theepan Moorthy and Andy Ye,
"A Scalable Computing and Memory Architecture for Variable Block Size
Motion Estimation on Field-Programmable Gate Arrays," Proceedings of the
2008 IEEE 18th International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, September 2008, pp. 83-88. [PDF]
·
P.
Chen and A. Ye, “The Effect of Sparse Switch Patterns
on the Area Efficiency of Multi-Bit Routing Resources in Field-Programmable
Gate Arrays,” Proceedings of the 2008 IEEE 18th International Conference on Field
Programmable Logic and Applications, Heidelberg, Germany, September 2008, pp.
427–430. (Short Paper). [PDF]
·
Andy
Ye and Jonathan Rose, "Using Bus-Based Connections to Improve
Field-Programmable Gate-Array Density for Implementing Datapath Circuits,"
IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 5, May
2006, pp. 462-473. [PDF]
·
Andy
Ye and Jonathan Rose, "Measuring and Utilising
the Correlation Between Signal Connectivity and Signal Positioning for FPGAs
Containing Multi-Bit Building Blocks," IEE Proceedings Computers &
Digital Techniques, Vol. 153, No. 3, May 2006, pp. 146-156. [PDF]
·
Andy
Ye and Jonathan Rose, "Measuring and Utilizing the Correlation Between
Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit
Building Blocks," Proceedings of the 2005 IEEE 15th International
Conference on Field Programmable Logic and Applications, Tampere, Finland,
August 2005, pp. 159-166. [PDF]
·
Andy
Ye and Jonathan Rose, "Using Bus-Based Connections to Improve
Field-Programmable Gate Array Density for Implementing Datapath Circuits,"
Proceedings of the 2005 ACM/SIGDA 13th International Symposium on
Field-Programmable Gate Arrays, Monterey, CA, February 2005, pp. 3-13. [PDF]
·
Andy
Ye and Jonathan Rose, "Using Multi-Bit Logic Blocks and Automated Packing
to Improve Field-Programmable Gate Array Density for Implementing Datapath
Circuits," Proceedings of the 2004 IEEE Third International Conference on
Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 129-136.
[PDF]
·
Andy
Ye, Jonathan Rose, and David Lewis, "Architecture of Datapath-Oriented
Coarse-Grain Logic and Routing for FPGAs," Proceedings of the 25th IEEE
Custom Integrated Circuits Conference 2003, San Jose, CA, September 2003, pp.
61-64. [PDF]
·
Andy
Ye, Jonathan Rose, and David Lewis, "Synthesizing Datapath Circuits for
FPGAs with Emphasis on Area Minimization," Proceedings of the 2002 IEEE
First International Conference on Field-Programmable Technology, Hong Kong,
December 2002, pp. 219-226. [PDF]
·
Andy
Ye and David M. Lewis, "Procedural Texture Mapping on FPGAs,"
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on
Field-Programmable Gate Arrays, Monterey, CA, February 1999, pp. 112-120. [PDF] (Colour Version [PDF])
·
Mousa Al-Qawasmi and Andy Ye,
"An Investigation of the Accuracy of the VPR and COFFE Area Models in Predicting the Layout Area of FPGA Lookup Tables,"
Proceedings of the IEEE SoutheastCon 2020,
Raleigh, NC,
March 2020,
pp 1-9.
·
Julien Li-Chee-Ming, Zheng Wu, Randy Tan, Ryan Tan, Naimul Mefraz Khan, Andy Ye and Ling Guan,
"A Scene-Based Augmented Reality Framework for Exhibits,"
Proceedings of the 16th International Conference on Image Analysis and Recognition,
Waterloo, Ontario,
August 2019,
pp 287-296.
·
Andy Ye and Karthik Ganesan,
"Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors,"
Proceeding of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Monterey CA,
February 2017,
pp 285,
(Poster).
·
Farheen Khan and Andy Ye,
"An Empirical Analysis of the Fidelity of VPR Area Models,” Proceedings
of 2016 IEEE 24th International Symposium on Field-Programmable Custom Computing Machines, Washington DC, May 2016, pp 138, (Poster, Acceptance Rate: 40% Long Paper, Short Papr and Poster combined).
·
Hamid Asefi, Behnaz Ghoraani, Andy Ye, and Sri
Krishnan, "Hardware-Software Analysis of Pole Model Features,” Proceedings
of the 2011 IEEE 24th Canadian Conference on Electrical and Computer
Engineering, Niagara Falls, Ontario, May 2011, pp. 1288-1291.
·
Hamid Asefi, Behnaz Ghoraani, Andy Ye, and Sri
Krishnan, "Audio Scene Analysis using Parametric Signal Features,” Proceedings
of the 2011 IEEE 24th Canadian Conference on Electrical and Computer
Engineering, Niagara Falls, Ontario, May 2011, pp. 922-925.
·
Jasmina Vasiljevic and Andy
Ye, "A Study on the Scalability of the H.264/AVC Fractional Motion
Estimation Algorithm on FPGAs," Proceedings of the 2010 IEEE 18th
Symposium on Field Programmable Custom Computing Machines, Charlotte, North
Carolina, May 2010, pp. 283. (Poster)
·
Jasmina Vasiljevic and Andy
Ye, "A Scalability Study of Fractional Motion Estimation for H.264
Encoding," Proceedings of the 2010 IEEE 18th Canadian Conference on
Electrical and Computer Engineering, Calgary, Alberta, May 2010, pp. 1-5.
·
Theepan Moorthy and Andy Ye,
"A Scalable Architecture for Variable Block Size Motion Estimation on
Field-Programmable Gate Arrays," Proceedings of the 2008 IEEE 16th
Canadian Conference on Electrical and Computer Engineering, Niagara Falls,
Canada, May 2008, pp. 1303-1308. [PDF]
·
Andy
Ye and David M. Lewis, "Procedural Texture Mapping Using the Transmogrifier-2,"
Micronet Conference, Ottawa, Ontario, 1999. [PDF]
·
Andy
Ye and David M. Lewis, "Procedural Texture Mapping Using Transmogrifier-2:
An Initial Study," University of Toronto Field Programmable Gate Array
Research Retreat, Toronto, Ontario, June 1997.
·
Andy
Ye, “Minimum-Area IIB – How to Minimize the Area of a Logic Cluster without
Losing any Functionality?”, University of British Columbia
Cascadia Workshop, Vancouver, British Columbia,
August 13, 2010. [PDF]
·
Andy
Ye, "Using the Minimum Set of Input Combinations to Minimize the Area of
Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os
in FPGAs," University of Toronto FPGA Research Seminar, Toronto, Ontario,
October 15, 2009.
·
Phoebe
Ping Chen and Andy Ye, "FPGA Routing Architectures for Datapath
Circuits," University of Toronto FPGA Research Seminar, Toronto, Ontario,
May 15, 2008.
·
Theepan Moorthy and Andy Ye,
"FPGA Hardware Acceleration for H.264 Motion Estimation," University
of Toronto FPGA Research Seminar, Toronto, Ontario, April 17, 2008.
·
A.
Ye and J. Rose, "Using Bus-Based Connections to Improve FPGA Density for
Implementing Datapath Circuits," Connections 2005 Research Review,
University of Toronto, Toronto, Ontario, June 2005.
·
Andy
Ye, Jonathan Rose, and David M. Lewis, "Field-programmable Gate Array
Architectures and Algorithms Optimized for Implementing Datapath
Circuits," Xilinx Inc., Toronto, Ontario, February 27, 2004. [PowerPoint]
·
Andy
Ye, Jonathan Rose, and David M. Lewis, "Architecture of Datapath-Oriented
Coarse-Grain Logic and Routing for FPGAs," Altera Corp., Toronto, Ontario,
October 9, 2003. [PowerPoint]
·
Andy
Ye, Jonathan Rose, and David M. Lewis, "Architecture of Datapath-Oriented
Coarse-Grain Logic and Routing for FPGAs," Xilinx Inc., Toronto, Ontario,
July 2003. [PowerPoint]
·
Andy
Ye, David M. Lewis, and Jonathan Rose, "Synthesizing Datapath Circuits for
FPGAs with Emphasis on Area Minimization," Xilinx Inc., Toronto, Ontario,
July 2002. [PowerPoint]
·
Andy
Ye and David M. Lewis, "Procedural Texture Mapping Using FPGAs," ATI
Technologies Inc., Thornhill, Ontario, August 1997. [PDF]
·
Andy
Ye (supervised by Jonathan Rose and David Lewis), "Field-Programmable Gate
Array Architectures and Algorithms Optimized for Implementing Datapath
Circuits," Ph.D. Thesis, Edward S. Rogers Sr. Department of Electrical and
Computer Engineering, University of Toronto, November 2004. [PDF]
·
Andy
Ye, "Ph.D. Progress Report --- Report #3," Ph.D. Thesis Monitoring
Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering,
University of Toronto, May 2003. [PDF]
·
Andy
Ye, "Ph.D. Progress Report --- Report #2," Ph.D. Thesis Monitoring
Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering,
University of Toronto, May 2002. [PDF]
·
Andy
Ye, "Ph.D. Progress Report --- Report #1," Ph.D. Thesis Monitoring
Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering,
University of Toronto, August 2001. [PDF]
·
Andy
Ye, David M. Lewis, "Ph.D. Thesis Proposal: Routing Architecture and Place
and Route Tools for DP-FPGA," Ph.D. Thesis Proposal, Edward S. Rogers Sr.
Department of Electrical and Computer Engineering, University of Toronto, July
2000. [PDF]
·
Andy
Ye (supervised by David M. Lewis), "Procedural Texture Mapping on
FPGAs," M.A.Sc. Thesis, Edward S. Rogers Sr. Department of Electrical and
Computer Engineering, University of Toronto, 1999. [PDF]
·
Andy
Ye (supervised by Raymond H. Kwong), "Analyzing
and Designing Linear Quadratic Gaussian Controllers for a Dual Link Flexible
System," B.A.Sc. Thesis, Edward S. Rogers Sr. Department of Electrical and
Computer Engineering, University of Toronto, 1996.
·
M.T.
Ghorab, S.B. Prubhu, and A.
Ye, ELE202: Electric Circuits Lab Manual [ELE202 Lab Manual]
·
Vincent
C. Gaudet, Andy Ye, David M. Lewis, and Fred Aulich, "University of Toronto Ultragizmo
Board: Tutorials, Experiments, and Laboratory Notes Version 3," Lab
Manual, Edward S. Rogers Sr. Department of Electrical and Computer Engineering,
University of Toronto, 2000. [The Ultragizmo
Manual]
·
ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays
·
International Conference on
Field-Programmable Logic, Reconfigurable Computing, and Applications
·
IEEE International Conference on Field-Programmable
Technology