Farheen Fatima Khan

Ryerson University
Department of Electrical & Computer Engineering,
350 Victoria Street
Toronto, ON, Canada
M5B 2K3
farheenfatima.khan@ryerson.ca

Biography :

I  fininshed my Ph.D in  Electrical & Computer Engineering from Ryerson University in 2017.  Where I  researched  Field programmable gate array (FPGA)  architectures and area modelling of FPGA components under the supervision of Andy Ye. I received my M.Tech in Computer Science Engineering and B.Tech in Electronic and Communication Engineering, both from J.N.T.U (Jawaharlal Nehru Technological University) Hyderabad, India.

Research Interests:

•       Field Programmable Gate Array (FPGA) architectures

•       Layout and area estimation of FPGA components

•        Computer-Aided Design (CAD) tools for FPGAs

Research:

•       Research deals with FPGA architectures, whose overarching aim is to determine which specific circuit structures offer the best speed, area, power for a set of benchmark applications.

•       Modelling of FPGA area.

•       Through detailed layout of typical FPGA structures, showed that the conventional models often over/under estimate the actual area consumption.

•       Proposed new area models for FPGA based components which offer more accuracy, as well as higher fidelity versus the state-of-the-art.

Download:

If you are interested and would like to download the layout information of FPGA components. [click here]

Publications:

Peer- Reviewed Journal Papers

•        Farheen.Khan and Andy.Ye, “A Study on the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area”, Elsevier Microprocessors and Microsystems – Embedded Hardware Design, vol 52, pp. 287- 298, July 2017.

•        Farheen.Khan and Andy.Ye, “An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures”, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (under revision).

Peer- Reviewed Conferences  Papers

•        Farheen.Khan and Andy.Ye, “An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures”, 26th International Conference on Field Programmable Logic and Applications (FPL), Lausanne, 2016, pp. 1-11, Sep. 2016. (Best Paper Award) [Acceptance rate: 21%]. [web]

•        Farheen.Khan and Andy.Ye, “An Empirical Analysis of the Fidelity of VPR Area Models”, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, pp 138, May 2016. [Poster acceptance rate: 40%]. 

 

•        Farheen.Khan and Andy.Ye, “Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area”, 23rd IEEE International Symposium on  Field-Programmable Custom Computing Machines, pp. 223-226, May 2015. [Short paper acceptance rate: 38.9 %].