 |
350 Victoria St. Toronto, Ontario CANADA M5B 2K3 Telephone: +(416) 979 5000 ext. 556084, Fax: +(416) 979 5280 |
| |
350 Victoria St. Toronto, Ontario CANADA M5B 2K3 Telephone: +(416) 979 5000 ext. 556084, Fax: +(416) 979 5280 |
|
|
|
|
Citations |
List of Alumni |
|
Research projects related
to GPU-based Heterogeneous Systems and Application
Profiling & Auto-tuning.
Teaching COE838 and EE8221 (Systems on Chip Design)
courses in Winter 2024.
Consultation Hours: by appointment
(Office ENG 448)
Lecture Courses (Teaching Material):
COE718 Embedded System Design
EE8205 Embedded Computer Systems
COE838 Systems-on-Chip Design
EE8221 Systems-on-Chip
Design
Computer Organization and
Architecture
Real-time Operating Systems
Undergraduate Capstone Design Projects:
Design and FPGA-based Implementation
of Cryptocurrency Mining Techniques
Design of an NoC based Multimedia
System-on-Chip
Gate Reminder for a Smart Home
PCI-Express Interface Design and
Implementation for ARM Cortex CPU
CPU-GPU Implementation of Collision
Detection for Gaming Applications
HDL Implementation of SATA I/O
Protocol on a FPGA-based System
Hardware (RTL) Design of Secure Hash
Functions for Crypto-currency Mining
Design and FPGA Implementation of
2D-NoC based System-on-Chip
Authentication and Secure Data
Exchange for Smart RF (Tag/Card) Systems
Current Research Interests: CPU-GPU based Heterogeneous Systems, Auto-Tuning
Tools for GPU-based Heterogeneous Systems, System-on-Chip,
Network-on-Chip (NoC), NoC Synthesis and
Design, Hardware/Software Co-design, Real-time Embedded Systems,
Intelligent System, Smart
RFID Systems, Authentication Protocols.
Design and Research Projects:
CAD tools for CPU-GPU/GPGPU Systems
and CPU-GPU based Heterogeneous Computing.
Profiling, Auto-Tuning
and Application Partitioning for CPU-GPU Systems
CAD tools for Network-on-Chip Synthesis and Design.
Design of an Efficient
and High Performance NoC Router or NoC with Minimal
(optimal) Latency, Power and Chip area.
NoC Topology Generation and Analysis
for High Performance MPSOCs
Co-synthesis of Heterogeneous
Multi-Task Embedded Systems with Real Time Constraints
Associate Editor:
1.
Int. Journal Embedded and Real-Time Communication Systems
(IJRETCS)
2. Int.
Journal of Reconfigurable and Embedded Systems (IJRES)
Embedded
and Networking Systems: Design, Software and Implementation
, Eds. Gul Khan and Kris Iniewski, (CRC Press) Taylor &
Francis, 2014
Recent and
Selected Publications: See also
Gul Khan at Google Scholar
GPU
Auto-tuning Framework for Optimal
Performance and Power Consumption,
GPGPU '23: 15th Workshop on
General Purpose Processing Using
GPU, Montreal, Canada,
February 2023
download
An
8‐bit digital‐to‐time converter with pre‐skewing
and time interpolation,
IET
Circuits, Devices & Systems, 2021
download
Reconfigurable
On-Chip Interconnection Networks for High
Performance Embedded SoC Design, Journal
of Systems Architecture, Vol.
106, June
2020
download
Heterogeneous
Design and Efficient CPU-GPU Implementation of
Collision Detection,
IADIS
International Journal on Computer Science and
Information Systems, Vol
14, No. 2, pp. 25-40, July-Dec,
2019 download
Efficient
and Low Power NoC Router Architecture,
in
High-Speed & Low Power Technologies:
Electronics and Photonics, 2018 Taylor
& Francis
chap-9 download
Application
Mapping to Mesh NoCs using a Tabu Search
based Swarm Optimization, Microprocessors
&
Microsystems,
Vol. 55, Nov.
2017
download
Efficient
Dynamic Virtual Channel Organization and
Architectures for NoC Systems,
IEEE Trans. VLSI Systems, Vol 24, No. 2,
February 2016
download
Low
Cost Authentication Protocol Scheme for Passive,
Computational Capable RFID Tags,
Wireless
Networks, Vol.
21, No. 2, 2015
download
Statically adaptive multi-FIFO
buffer Architecture
for Network-on-Chip, Microprocessors
& Microsystems, Vol. 39, No. 1, 2015
download
High Performance NoC synthesis using analytical
modelling and simulation, Journal
of Systems Architecture,
Vol. 59, No. 7, 2013
download
Secure
Authentication Scheme for Passive C1G2 RFID Tags,
Computer
Networks Vol. 56, No. 1, 2012
download
Designing
Power and Performance Optimal Application-specific
Network-on-Chip Architecture, Microprocessors
& Microsystems, Vol. 35, No. 6, 2011
download
A
Modeling tool for Simulating & Design of On-chip
Network Systems,
Microprocessors & Microsystems, Vol 34, No
3-4, 2010
download
Throughput-Oriented
NoC Topology Generation and Analysis for High
Performance SoCs,
IEEE Trans. VLSI Systems, Vol 17, No. 4, 2009
download
CAD
tool for Hardware Software Co-synthesis of
Heterogeneous Multiple Processor Embedded
Architectures,
download
