Fei Yuan
VLSI
Analog-to-digital converters (ADCs) are an essential block of wireless communication systems such as cellular phones and wireless sensors and sensor networks. ADCs are representative mixed-mode systems as both analog and digital circuits co-exist. Although the scaling of CMOS technology has greatly improved the switching time and timing resolution of digital circuits, the performance analog circuits degraded greatly at the same time mainly due to a reduced voltage headroom and worsen linearity. It is highly desirable to have mixed-mode systems such as ADCs realized using digital circuits only such that the full merits of technology scaling such as programmasbility, portability, and immunity to noise and disturbance, to name a few, can be utilized.
This capstone design project will design a 2nd-order all-digital delta-sigma analog-to-digital converter for wireless sensors. The ADC will be designed in a 65 nm CMOS technology with full silicon realization (layout) .
1. 2nd-order low-power all-digital oversampling delta-sigma analog-to-digital converter for wireless sensor applications designed in a 65 nm CMOS technology.
2. Three key subsystems of the ADC include (i) An all-digital phase-locked loop that provides the system clock of the ADC. (ii) An all-digital 2nd-order delta-sigma modulator, and (iii) A decimation filter.
The analog-to-digital converter will consists of three subsystems : (i) An all-digital phase-locked loop that provides the system clock of the ADC. (ii) An all-digital 2nd-order delta-sigma modulator realized using a time-mode approach, and (iii) A decimation low-pass filter that filters out displaced excessive quantization noise and extracts the wanted signal.
1. Thorough understand the principle of delta-sigma modulators, phase-locked loops, and decimation low-pass filters. 2. Find a wireless sensor application so as to determine the design specifications of the ADC.
Design an all-digital phase-locked loop that provides the system clock of the ADC in a 65 nm CMOS technology. The all-digital phase-locked loop consists of a time-to-digital converter (TDC) phase quantizer, a FIR (finite-impulse-response) low-pass filter, and a digitally-controlled oscillator (DCO). The student is required to (i) Acquire the in-depth knowledge of basic TDCs, FIR filters, and DCOs. (ii) Design, analyze, simulate, and quantify the TDC phase quantizer. (iii) Design, analyze, simulate, and quantify the FIR low-pass filter. (iv) Design, analyze, simulate, and quantify the DCO. (v) Design, analyze, simulate, and quantify the all-digital PLL. (vi) Silicon implementation of the PLL (layout).
Design an all-digital 2nd-order delta-sigma modulator in a 65 nm CMOS technology. Time-mode approaches will be used to realized the modulator. The all-digital delta-sigma modulator consists of time adders, time integrators, time quantizers, and digital-to-time converters (DTCs). The student is required to (i) Acquire the in-depth knowledge of time-mode signal processing. (ii) Design, analyze, simulate, and quantify time adders. (iii) Design, analyze, simulate, and quantify the time integrators. (vi) Design, analyze, simulate, and quantify the time quantizers. (v) Design, analyze, simulate, and quantify the digital-to-time converters. (vi) Design, analyze, simulate, and quantify the delta-sigma modulator. (vii) Silicon implementation of the modulator (layout).
Design a low-pass decimation filter in a 65 nm CMOS technology. The student is required to (i) Acquire the in-depth knowledge of decimation and decimation filter. (ii) Select a specific decimation filter suitable for the application. (iii) Design, analyze, simulate, and quantify the decimation filter. (iv) Silicon implementation of the decimation filter (layout).
Students A and B must take ELE724. Student C must take either ELE724 or ELE734.
FY01: Low Power All-Digital Analog-to-Digital Converters for Wireless Applications | Fei Yuan | Friday September 15th 2017 at 03:18 PM