Adaptive SerDes for Multi-Gbps Data Links with 4-PAM Signaling

2017 ELE Engineering Design Project (FY03)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

VLSI

Preamble

Data intensive applications require data be transmitted among chips, modules, and chassis via wire channels such as on-chip interconnects and printed circuit board traces at tens of giga-bit-per-second (Gbps) per channel. Gbps data transmission over wire channel is at the heart of emerging applications such as cloud computing, computer networks, and data centers, to name a few. The data rate of serial links is limited by inter-symbol interference (ISI) arising from channel impairments with finite bandwidth, reflection, and crosstalk the most critical. Decision feedback equalization (DFE) that eliminates ISI by minimizing the power of the difference between desired and equalized data symbols is the most robust and widely used nonlinear post-equalization technique. This capstone design project designs an adaptive SerDes with 4PAM (pulse-amplitude-modulation) signaling.

Objective

Designs a 10 Gbps adaptive SerDes with 4PAM signaling in a 65 nm CMOS technology.

Partial Specifications

Designs a 10 Gbps adaptive SerDes with 4PAM signaling in a 65 nm CMOS technology. The SerDes consists of (i) a 4PAM transmitter, (ii) a continuous-time linear equalizer (CTLE), (iii) a decision feedback equalizer, and (iv) clock and data recovery system.

Suggested Approach

- Extensive reading on serial links and their emerging applications.
- Thoroughly understanding ISI, eye-diagram, and BER of serial links.
- Thoroughly understanding 4PAM, SerDes, CTLE, DFE, adaptive DFE, and clock recovery using phase-locked loops (PLLs).
-Thoroughly understanding data-DFE and edge-DFE.
- Materials are to be provided by Prof. Fei Yuan.

Group Responsibilities

Thoroughly understanding ISI, eye-diagram, BER, 4PAM, SerDes, CTLE, DFE, adaptive DFE, and clock recovery using phase-locked loops (PLLs), data-DFE and edge-DFE.

Student A Responsibilities

(1) Design of a 4PAM transmitter, which includes a pseudo-random bit sequence (PRBS) generator using shift-registers, (ii) a pre-emphasis block, (iii) a current-mode driver, and (iv) a PLL with a fixed frequency reference. (2) Full schematic implementation of the above blocks and quantify their performance. (3) Full silicon implementation of the above blocks.

Student B Responsibilities

(1) Design of a CTLE and (ii) an adaptive edge DFE. (2) Full schematic implementation of the above blocks and quantify their performance. (3) Full silicon implementation of the above blocks.

Student C Responsibilities

(1) Design of a PLL-based clock recovery system, which includes (i) a frequency lock loop that locks to an external frequency reference, (ii) a phase-locked loop that locks to the edge of equalized data (2) Full schematic implementation of the above blocks and quantify their performance. (3) Full silicon implementation of the above blocks.

Course Co-requisites

ELE724 or ELE734. All students must have ELE863