Gul Khan
FPGA / Reconfigurable Computing
NoC (Network-on-Chip) interconnects have transpired in response to the performance limitations and overhead of bus-based systems in Multi-Processor System-on-Chip (SoC) architectures. NoCs replace the buses with routers and links, where packets communicate simultaneously between on-chip cores to improve overall system performance. A traditional way to alleviate contention in NoC systems is to use virtual channel (VC). In conventional VC method, a physical channel support several virtual channels that are multiplexed across the physical channel. Virtual channels are also used to improve message latency and NoC throughput. By allowing messages to share a physical channel, messages can make progress rather than remain blocked, leading to high performance NoC communication. NoC router is the main IP core that facilitate the implementation of an NoC based SoC for Multimedia applications.
Investigate, design and develop an NoC router core (IP) for NoC based System-on- Programmable Chip (SoPC). NoC implementation of a typical Multimedia application.
1. Study of NoC systems.
2. Investigation of the design of an NoC router.
3. Selection of a typical Multimedia application for multi-core NoC system.
4. Design and implement a NoC router core suitable for NoC based systems.
5. Verify the router core by prototyping a Multi-core NoC system using the soft
CPU cores and other accelerator IPs for a typical application.
1. Study of Soft processor core architectures & programming models, and exploring Altera Cyclone IV/V FPGA based environment for developing embedded NoC systems.
2. Explore various on-chip routing techniques.
3. Investigation of the architecture and specification of various network routers suitable for NoC systems.
4. Prototyping an NoC router for a well known NoC topology such as 2D-mesh
5. Implementation of an NoC system application by employing the developed network router core.
1. Study Nios-II (or microblaze, ARM A9) processor architecture and programming model as well as FPGA based (Cyclone) embedded platform for some typical NoC applications. 2. Investigate the results of the development being carried out by various groups working on an SoC based NoC router IPs. 3. Develop a detailed specification of an NoC router for some relevant NoC application. 4. Design, develop, implement and prototype the NoC router on an FPGA based platform. 5. Verify the NoC router by utilizing it in a typical NoC prototype.
1. Study some candidate SoPC-based embedded platform for NoC implementation. 2. Investigate and study the various NoC router architectures for implementation. 3. Design and write the NoC router specification in a high level language (e.g. SystemC) suitable for NoC systems. 4. Develop the network router for NoC by working with Student B. 5. Assist Student B and C and manage the overall project design and implementation.
1. Investigate some candidate Nios-II/microblaze/ARM-A9 processor-based embedded platforms. 2. Improve the specification (prepared by student A) and develop the NoC router. 3. Overall design of an NoC system by employing the NoC router for a typical NoC application with the help of student C. 4. Assist Student A and C to manage the overall project design and implementation.
1. Study some multi-core embedded platform developed for typical multimedia applications. 2. Employ the simple NoC router to establish communication between routers. 3. Design and establish communication between a CPU (source or destination) core and the memory core. 4. Assist Student A and B to manage the overall project design and implementation.
COE718, COE838
GK01: Design and Prototyping a NoC based System-on-Chip for Multimedia Applications | Gul Khan | Not yet submitted at No time