Accelerator based System on Chip Design for Embedded Applications

2017 ELE Engineering Design Project (GK02)

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Faculty Lab Coordinator

Gul Khan

Topic Category

VLSI

Preamble

On-Chip buses are an commonly used to interconnect multiple cores of a System-on-Chip (SoC) design. The performance limitations and overhead of bus-based systems are to be studied for Multi-Processor System-on-Chip (SoC) architectures. Avalon and IBM core-connect are some typical on-chip bus IPs available for FPGA devices. To facilitate the implementation of a high performance embedded application, accelerator based IPs need to be designed and used in place of general purpose CPU cores.

Objective

Study, design and develop an accelerator based System on Programmable Chip (SoPC). An on-chip bus-based SoC Implementation of a typical embedded application.

Partial Specifications

1. Study of various System-on-Chip (SoCs).
2. Selection of a typical Multimedia application for multiple IP core SoC.
3. Design and implement an SoC for the embedded application employing bus-based interconnection such as Avalon, AMBA or Core-connect.
4. Verify the SoC using a CPU and accelerator IP cores.

Suggested Approach

1. Study of processor IP core architectures & programming models and explore Altera Cyclone (IV/V) FPGA based platform for developing embedded SoCs.
2. Investigate an on-chip interconnection techniques and study the architecture of various accelerators suitable for SoC systems.
3. Design and prototype the accelerator IP suitable for the application.
4. Implementation of the embedded SoC for the selected application by employing the developed accelerator and CPU IP cores.

Group Responsibilities

1. Study soft CPU (Nios-II, micro-blaze, ARM-A9, etc.) processor cores and their programming model. 2. Identify a suitable FPGA based (Cyclone IV or V) platform suitable to implement embedded applications. 3. Develop a detailed specification of an accelerator for some relevant embedded SoC applications. 4. Prototype the accelerator on an FPGA based platform. 5. Design and implement the accelerator based SoC for the embedded application.

Student A Responsibilities

1. Study some candidate FPGA platform for embedded SoC implementation. 2. Investigate and study various bus-based SoC architectures for implementation. 3. Develop the accelerator specification in a high level language (e.g. SystemC, System Verilog) suitable for SoC systems. 4. Develop the accelerator IP for SoC by working with Student B. 5. Assist Student B and C and manage the overall SoC design and implementation.

Student B Responsibilities

1. Investigate some candidate Nios-II/microblaze/A9 processor-based embedded platforms. 2. Improve the specification (prepared by student A) and develop the on-chip bus based accelerator IP. 3. Design an SoC by employing the accelerator for a typical embedded application with the help of student C. 4. Assist Student A and C to manage the overall SoC project design and implementation.

Student C Responsibilities

1. Study some multi-core embedded platform developed for multimedia or other applications. 2. Employ a simple accelerator IP to establish a bus-based communication between the CPU and accelerator IP cores. 3. Design and establish communication among CPU, accelerator and memory cores by employing on-chip bus interconnection. 4. Assist Student A and B to manage the overall project design and implementation.

Course Co-requisites

COE718