Gul Khan
Software / Intelligent Instrumentation
On-Chip buses are an important interconnection for embedded System-on-Chips (SoC). The performance limitations and overhead of bus-based systems need to be investigated for Multi-core Embedded System-on-Chip (SoC) architectures. AMBA, Avalon and IBM core-connect are some typical on-chip buses. To facilitate and implement a high performance embedded application, accelerator IPs need to be designed and employed rather than employing one or multiple general purpose processor cores.
Investigate, design and develop an accelerator based Embedded System on Programmable Chip (SoPC). An on-chip bus-based SoC Implementation of a selected Multimedia, Encryption or Biomedical Instrumentation application.
1. Study of various Embedded SoCs (System-on-Chip).
2. Investigation of the design of an Embedded SoC.
3. Selection of a Multimedia/Encryption/Biomedical instrumentation application suitable for multi-core implementation.
4. Design and implement an SoC for the selected embedded application employing on-chip bus (such as Avalon, AMBA or IBM Core-connect bus).
5. Verify the the SoC using the soft CPU cores and accelerator IPs for a typical
embedded application.
Suggested Approach
1. Study of processor core architectures & programming models, and exploring Altera Cyclone IV/V FPGA based environment for developing embedded SoCs.
2. Explore various on-chip interconnection techniques.
3. Investigation of the architecture and specification of various SoC accelerators suitable for embedded systems.
4. Prototyping an accelerator for a typical embedded Multimedia/Encryption/Biomedical instrumentation application.
5. Implementation of Embedded SoC by employing the developed accelerator IP and CPU cores.
1. Study soft CPU Nios-II (ARM-A9, etc.) processor architecture and programming model as well as FPGA based (Cyclone IV/V) embedded platform for typical embedded applications. 2. Investigate the results of the development being carried out by various industrial and academic groups working on accelerator based embedded SoCs. 3. Develop a detailed specification of an accelerator IP for relevant embedded SoC applications. 4. Design, develop, implement and prototype the accelerator on an FPGA based platform. 5. Design and verify the embedded SoC for the Multimedia/Encryption or Biomedical instrumentation application.
1. Study some candidate SoPC-based embedded platform for the implementation of embedded system. 2. Investigate and study various bus-based SoC architectures for implementation. 3. Design and write the accelerator IP specification in a high level language (e.g. SystemC, System Verilog) suitable for the proposed System on Chip. 4. Develop the accelerator IP for the SoC by working with Student-B. 5. Assist Student B and C and manage the overall embedded project design and implementation.
1. Investigate some candidate Nios-II/microblaze/A9 processor-based embedded platforms. 2. Improve the specification (prepared by student A) and develop the on-chip bus based accelerator IP. 3. Overall design of an SoC system by employing the accelerator IP for the selected embedded application with the help of student C. 4. Assist Student A and C to manage the overall embedded SoC project design and implementation.
1. Study some multi-core embedded platform developed for typical multimedia, encryption or biomedical instrumentation applications. 2. Employ the simple accelerator to establish a bus-based communication between the soft CPU and the accelerator IP. 3. Design and establish communication between a CPU core, accelerator and memory cores by employing an on-chip bus interconnection. 4. Assist Student A and B to manage the overall project design and implementation.
COE718, COE838
GK04: Design and Implement an Accelerator based High Performance Embeddedd SoC | Gul Khan | Not yet submitted at No time