Reconfigurable Computing to Accelerate Arithmetic Operations for Applications

2017 COE Engineering Design Project (NM09)

Faculty Lab Coordinator

Nagi Mekhiel

Topic Category

FPGA / Reconfigurable Computing


Reconfigurable Computing is now available at low cost and used to run applications that need more computing power for specific arithmetic operations using hardware in FPGA. There are important applications in multimedia to sharpen images or blur them that need massive calculations on small data sizes suitable for many ALUs implemented in FPGA. Reconfigurable hardware can be used solely to build functional units that may be used as a coprocessor. A coprocessor is in general larger than a functional unit, and is able to perform computations without the host processor. Instead, the processor initializes the reconfigurable hardware and either sends the necessary data to the logic, or provides information on where this data might be found in memory. The project will enable students to build a reconfigurable computer using available off shelves computers and FPGA then select an application that needs the accelerator in FPGA. Students will learn also how to write efficient RTL code for FPGA that targets the specific portion of application that needs hardware accelerator, they built and measure the performance improvements and know how to deal with performance limitations.


To build a real reconfigurable computer, then write efficient code that improves the performance of an application which requires significant hardware resources to run fast in FPGA. The performance bottleneck and limitation must be explained and identified.

Partial Specifications

-Host Computer with multi-core
-The application must need many simple operations to run in FPGA that will be implemented in many ALUs
-FPGA is connected to host Computer to program it and download data
-Use suitable software tools to program and reconfigure FPGA

Suggested Approach

-Download required Software for FPGA.
-Your project must identify which portion of application needs to Run in FPGA.
-Use FPGA as an accelerator to host computer and identify how the host communicate with accelerator to send Data to be accelerated and results be returned back.
-Evaluate performance gain from reconfigurable computing
Useful links:

Group Responsibilities

The group is responsible to work to achieve the following:- -Selecting the Application that requires reconfigurable computing power -Read all references related about the application and why it requires the reconfigurable computer -Select a suitable host computer -Select OS to be used -Install software for the FPGA -Write efficient code for application -Define performance issues, bottleneck and try to eliminate it -Try to change the algorithm used for application to be suitable for FPGA Acceleration -Evaluate and measure performance gain and of system -write report of the findings and procedures for this project

Student A Responsibilities

-Reading about the application and collecting references about methods used to run it -Define acceleration code

Student B Responsibilities

-Identify a suitable FPGA tools and support to implement project -Install its software

Student C Responsibilities

-Define suitable algorithm for reconfigurable computing and optimize the code -measure performance of application and identify limitations and bottlenecks -Write report to explain project and achievement gained

Course Co-requisites


NM09: Reconfigurable Computing to Accelerate Arithmetic Operations for Applications | Nagi Mekhiel | Not yet submitted at No time