Implementation of an I/O protocol (SATA or PCI-e) for a FPGA board

2018 COE Engineering Design Project (GK02)

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Faculty Lab Coordinator

Gul Khan

Topic Category

FPGA / Reconfigurable Computing

Preamble

Expansion of an existing FPGA board to include some sophisticated hardware functionality required for a computational platform will be an interesting project. The expansion can be in terms of a storage controller or in general an I/O controller. The interface protocol that can be used will be either SATA or PCIe. Each interface will constitute a complete design project. The capstone design group is to choose a basic version of one of these two protocols for implementation, and design it by using Verilog or VHDL to complete an RTL IP of either SATA or PCIe controller. The design can be tested and verified using UVM and System-Verilog from the module to the System level. The designed RTL is to be prototyped on the FPGA and demonstrate through basic communication with a storage device for SATA such as hard disk or a PCIe based system.

Objective

RTL design and implementation of either SATA or PCIe protocol for an existing FPGA board.

Partial Specifications

1. Study of SATA or PCIe interface and its protocol for FPGA implementation.
2. Select one of the SATA or PCIe protocol for RTL implementation.
3. Use Verilog or VHDL (preferably Verilog) for hardware implementation of the protocol.
4. Synthesize the interface RTL design of the protocol and implement it for the target FPGA board.
5. Interface a storage device or PCIe based system with your newly designed interface.

Suggested Approach

1. Study various I/O protocols including SATA and PCI express and select one of these protocol for implementation.
2. Study and select various FPGA platforms for SATA or PCIe implementation.
3. Select either SATA or PCIe protocol.
4. Study Verilog for RTL (hardware) design of the selected I/O protocol.
5. Design and Implement (preferably Verilog based) the RTL of the protocol.
6. Synthesize your Verilog RTL design of the protocol and implement it on the FPGA platform.
7. Interface a storage (e.g. hard-disk) or a PCIe based system via the implemented protocol.

Group Responsibilities

1. Investigate and study various I/O protocols including SATA and PCI express. 2. Select either SATA or PCI express protocol. 3. Study various FPGA platforms for SATA or PCIe implementation and select a target FPGA board/platform. 4. Study Verilog or VHDL for RTL (hardware) design of the selected I/O protocol. 5. Design and Implement (preferably Verilog-based) the RTL of the protocol. 6. Synthesize the RTL design of the protocol and implement it on the FPGA platform. 7. For verification, interface a SATA hard-disk or a PCIe based system via the implemented protocol with the FPGA board.

Student A Responsibilities

1. Investigate and study various I/O protocols (including SATA and PCI express) for implementation. 2. Study a couple of suitable FPGA-based platform for the I/O protocol implementation. 3. Study Verilog or VHDL for RTL (hardware) design of the selected I/O protocol. 4. Develop part of the RTL hardware design of selected I/O protocols (either SATA or PCI express) using Verilog or VHDL. 5. Develop and synthesize the protocol RTL design by working with Student B for target FPGA platform. 6. Assist Student B and C and manage the overall project design and implementation.

Student B Responsibilities

1. Study a couple of suitable FPGA-based platform for the I/O protocol implementation. 2. Study Verilog or VHDL for RTL (hardware) design of the selected I/O protocol. 3. Improve the RTL hardware design of selected I/O protocol (prepared by student A) and develop the final RTL design. 4. Synthesize the protocol RTL design by working with Student A for the target FPGA platform. 5. Assist Student A and C to manage the overall project design and implementation.

Student C Responsibilities

1. Investigate some candidate FPGA boards and/or platforms. 2. Study the selected I/O protocols (including SATA and PCI express) for implementation. 3. Study Verilog or VHDL for RTL (hardware) design of the selected I/O protocol. 4. Participate in the RTL design of the protocol using Verilog or VHDL. 5. For verification, interface a SATA hard-disk or a PCIe based system via the implemented protocol with the FPGA board. 6. Assist Student A and B to manage the overall project and implementation.

Course Co-requisites

COE718, COE838