Hardware (RTL) Design of Secure Hash Functions for Cryptocurrency Mining

2018 COE Engineering Design Project (GK04)

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Faculty Lab Coordinator

Gul Khan

Topic Category

FPGA / Reconfigurable Computing

Preamble

Hardware design and FPGA implementation of SHA (secure hash algorithm) functions for crypto currencies. Such functions are also being employed in data mining and other related commercial applications. Hardware acceleration of such crypto techniques will enable faster and efficient crypto currency mining. It is a good practice to study the specification of SHA function, and hardware design by using an HDL (hardware description language) such as Verilog or VHDL preferably Verilog. Verify the design using testbench environment developed in UVM by or SystemC. Then synthesize the Verilog design and implement it for an FPGA platform. It is always useful to compare the efficiency of hardware design of crypto techniques with with the software implementation on a high-end CPU and/or OpenCL implementation for a typical CPU-GPU platform.

Objective

FPGA-based Hardware design and implementation of Secure Hash functions useful for Cryptocurrency mining.

Partial Specifications

1. Study of various SHA techniques and choose a cryptic function for hardware and/or software implementation.
2. Identify the time-consuming operation in cryptocurrency mining for hardware (FPGA) implementation
3. Use system-Verilog or VHDL (preferably Verilog) for hardware implementation.
4. Synthesize your Verilog design and implement it on the target FPGA platform.
5. Compare the Hash function efficiency with a high-end CPU or a GPU implementation.

Suggested Approach

1. Study SHA algorithms and any other cryptocurrency mining functions.
2. Select and study a few FPGA platforms for SHA implementation.
3. Study system-Verilog or VHDL (preferably Verilog) for RTL (hardware) design of SHA functions.
4. Software Implementation of the selected hash function for SystemC or OpenCL (for GPU implementation).
5. Design, verify and implement (preferably Verilog based) SHA algorithm.
6. Synthesize the Verilog RTL design of the cryptocurrency function and execute it on the FPGA platform.
7. Compare the execution with the software implementation on a high-end CPU or GPU based system.

Group Responsibilities

1. Study a few FPGA based platforms for SHA implementation. 2. Investigate various cryptocurrency SHA functions and choose a suitable function for FPGA implementation. 3. Study and learn System-Verilog (HDL) based hardware design. 4. Implement the SHA cryptocurrency algorithm using C or OpenCL (for GPU programming). 5. Hardware (RTL level) design and implementation of the selected cryptocurrency Hash function using System-Verilog or VHDL (preferably Verilog). 5. Synthesize and Verify your cryptocurrency function design and implement it for the target FPGA. 6. Compare the SHA cryptocurrency function execution time of your FPGA implementation with the software (CPU) or GPU implementation.

Student A Responsibilities

1. Investigate and study various SHA cryptocurrency functions for implementation. 2. Study a couple of FPGA platforms for cryptocurrency SHA function implementation. 3. Develop the hardware design of selected cryptocurrency SHA function using System-Verilog or Verilog. 4. Synthesize and verify SHA hardware design by working with Student B for target FPGA platform. 5. Compare the cryptocurrency SHA execution time of your hardware (FPGA based) design with the CPU or GPU implementation done by Student C. 6. Assist Student B and C and manage the overall project design and implementation.

Student B Responsibilities

1. Investigate some candidate GPU platforms. 2. Improve the cryptocurrency SHA hardware design (prepared by student A) and develop the final Verilog design. 3. Develop and synthesize the cryptocurrency SHA hardware design by working with Student A for target FPGA platform. 4. Compare the execution time of your SHA hardware (FPGA) design with the CPU or GPU implementation done by Student C. 5. Assist Student A and C to manage the overall project design and implementation.

Student C Responsibilities

1. Investigate some candidate high-end processor PC platforms capable of accommodating GPU board. 2. Implement the selected SHA cryptocurrency function in C or OpenCL for a high-end CPU or GPU implementation. 3. Participate in the hardware design of cryptocurrency SHA function using Verilog or VHDL. 4. Compare the cryptocurrency SHA execution time of your software (CPU) or GPU implementation with the hardware (FPGA) design prepared by student A and B. 5. Assist Student A and B to manage the overall project and implementation.

Course Co-requisites

COE718, COE838