FPGA/Hardware Design and Implementation of a Secure Hash (SHA) Function

2018 ELE Engineering Design Project (GK05)

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Faculty Lab Coordinator

Gul Khan

Topic Category

VLSI

Preamble

Hardware design and FPGA implementation of secure hash algorithm (SHA) including SHA or other crypto functions. Such crypto functions are used in data mining and other commercial applications. Hardware acceleration of these crypto functions to design efficient methodologies for faster data mining. It is a good practice to investigate and study the specification of various SHA functions, and design/implement the SHA function in hardware by using an HDL (hardware description language) such as Verilog. It is also a good practice to verify the design using a testbench environment developed in UVM using System-Verilog or in SystemC. Then synthesize and implement the design for the FPGA platform. It is always useful to compare the efficiency of hardware design of the SHA function with the software implementation of SHA function on a high-end CPU or with a parallel implementation in OpenCL for a CPU-GPU platform.

Objective

Hardware design and implementation on a FPGA platform for a popular SHA function used in data mining and other commercial applications.

Partial Specifications

1. Study various Hash and Cryptographic algorithms and choose a crypt0 technique for hardware and/or software (CPU) implementation.
2. Identify the most-time consuming operation in the Hash function for hardware (FPGA) implementation. A complete SHA function can also be implemented in hardware i.e. RTL.
3. Use VHDL or Verilog (preferably Verilog) for hardware implementation.
4. Synthesize the HDL design and implement on a suitable FPGA platform.
5. Compare the SHA function execution speed with software (C language) on a high-end CPU or OpenCL based GPU implementation.

Suggested Approach

1. Study SHA and various cryptographic functions.
2. Study and select a few Altera or Xilinx FPGA based platforms for SHA implementation in hardware.
3. Study System-Verilog (Verilog) or VHDL for hardware design of the SHA function.
4. Software Implementation of the selected hash function in SystemC or OpenCL.
5. Design and Implement (preferably Verilog-based) SHA function.
6. Synthesize the SHA RTL (e.g. Verilog) design and execute it on the FPGA platform.
7. Compare the execution time with the software implementation on a high-end CPU or a GPU platform.

Group Responsibilities

1. Study some suitable FPGA based platforms for SHA implementation. 2. Investigate various SHA and cryptographic functions and select a suitable function for FPGA implementation. 3. Study and learn System-Verilog (or VHDL) based hardware design methods. 4. Implement the SHA function using C for CPU implementation or OpenCL or GPU programming. 5. Hardware design of the selected hash function using System-Verilog or VHDL. 5. Synthesize and verify your SHA function design and implement it for the target FPGA platform. 6. Compare the SHA function execution timing of your design for software (C language) implementation or OpenCL for CPU and/or GPU implementation.

Student A Responsibilities

1. Study a couple of FPGA platforms for SHA implementation. 2. Investigate and study various SHA cryptic functions for implementation. 3. Hardware design of selected SHA function using System-Verilog or VHDL. 4. Develop and synthesize the SHA hardware (RTL) design by working with Student B for the FPGA platform. 5. Compare the SHA execution time of your hardware (FPGA) design with the software (CPU) or OpenCL based GPU implementation done by Student C. 6. Assist Student B and C and manage the overall project design and implementation.

Student B Responsibilities

1. Investigate some candidate GPU or high-end processor PC platforms. 2. Improve the SHA function RTL design (prepared by student A) and develop the final System-Verilog or VHDL design. 3. Verify and synthesize the SHA function hardware design by working with Student A for the target FPGA platform. 4. Compare the SHA execution time of your hardware (FPGA) RTL design with the software (CPU) or GPU implementation done by Student C. 5. Assist Student A and C to manage the overall project design and implementation.

Student C Responsibilities

1. Investigate some candidate GPU or high-end processor PC platforms. 2. Implement the selected SHA crypto function in C for a high-end CPU or OpenCL for GPU implementation. 3. Participate in the hardware design of SHA function (using System-Verilog or VHDL) being developed by Student A and B. 4. Compare the SHA execution time of your software (CPU) implementation or OpenCL GPU implementation with the hardware (FPGA) design. 5. Assist Student A and B to manage the overall project and implementation.

Course Co-requisites

COE718, COE838