Designing and Implementing a Low Power Adder for Future Chip-multiprocessors

2019 COE Engineering Design Project (FM03)

---

Faculty Lab Coordinator

Farah Mohammadi

Topic Category

FPGA and Reconfigurable Computing

Preamble

In nanometer electronics, leakage power depletes the power budget and has substantial contribution in overall power consumption. Methodologies such as power gating and reconfiguration are very useful to combat with increasing leakage power consumption in modern electronic systems. The design consists of two main parts: a hardware and a software. The hardware part consists of a reconfigurable adder implemented on FPGA that based on the situation switches between two modes, a low power adder and a high-power adder. The software part consists of a code that implements the reconfiguration between the two modes. In this project, heterogenous technologies such as CMOS, Nonvolatile, and other emerging technologies can be used.

Objective

- To design, develop and implement the reconfigurable hardware. - To apply heterogenous technologies such as CMOS, nonvolatile memory technologies to combat power consumption increase. - Calculating power consumption and performance of the implemented architecture. - Implementing the designed architecture on the FPGA.

Partial Specifications

• Design and develop a low power reconfigurable adder;

• Specify the technologies used in low power and high-power modes;

• Design a low power architecture with low leakage technology;

• Design a high-power architecture based on a technology with lower performance;

• Design and implement a reconfigurable methodology;

• Specify the characteristics of the used FPGA;

Suggested Approach

- Use off the shelve products such as PC, laptop, FPGA;
- Use reconfiguration techniques;
- Run simulations to ensure the system functionality;

Group Responsibilities

- Literature review on low power and reconfiguration techniques, different electronic technologies and FPGAs;
- Design/develop the technical specifications required for the memory architecture under consideration,
- Implement and test of the entire system with the above objectives,
- Prepare a technical report and present the results at the end of the program.

Student A Responsibilities

To design, develop and implement the hardware (FPGA implementation).

Student B Responsibilities

To design, develop and implement the hardware language code and algorithm for reconfiguration between low power and high-power modes.

Student C Responsibilities

To apply different low power technologies in designing the target architecture and choose the final technologies in two modes.

Student D Responsibilities

To develop design methodology for runtime reconfigurable FPGA

Course Co-requisites

Digital Systems, knowledge of Computer Architecture and FPGAs