Designing and Implementing a Cache Architecture for Future Multicore Systems

2019 COE Engineering Design Project (FM06)

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Faculty Lab Coordinator

Farah Mohammadi

Topic Category

Embedded Systems

Preamble

With increasing core count and parallelization of applications, this issue has become important that in future many-core architectures, workloads are expected to be large multithreaded and multiprogram applications. These large multithreaded and multiprogram applications need to access main memory through caches. Cache subsystems play a key role in performance and power consumption of future multicore systems in nanometer electronics. Methodologies such as power gating and reconfiguration are very useful to combat with increasing power consumption in modern electronic systems. The design consists of two main parts: a hardware and a software. Hardware part consists of a reconfigurable cache architecture implemented on FPGA that based on the situation switches between two modes, a low-power cache and a high-power cache. The software part consists of a code that implements the reconfiguration between the two modes. In this project, heterogenous technologies such as CMOS, nonvolatile memory, and other emerging technologies in the designed cache architecture can be used.

Objective

• To design, develop and implement the reconfigurable hardware (FPGA implementation). • To apply heterogenous technologies such as CMOS and nonvolatile memory technologies to combat increasing power consumption. • Calculating power consumption and performance of the implemented architecture. • Implementing the designed architecture on the FPGA.

Partial Specifications

• Design and develop a heterogenous low power reconfigurable last level cache architecture;

• Specify the technologies used in low power and high-power modes;

• Design a low power last level cache with low leakage technology;

• Design a high-power last level cache based on a technology with lower performance;

• Design and implement a reconfigurable methodology;

• Specify the characteristics of the used FPGA;

Suggested Approach

- Use off the shelve products such as PC, laptop, FPGA;
- Use reconfiguration techniques;
- Run simulations to ensure the system functionality;

Group Responsibilities

1. Literature review on low power and reconfiguration techniques, different electronic technologies and FPGAs;
2. Design/develop the technical specifications required for the system prototype under consideration,
3. Implement and test of the entire system with the above objectives,
4. Prepare a technical report and present the results at the end of the program.

Student A Responsibilities

To design, develop and implement the hardware (FPGA).

Student B Responsibilities

To design, develop and implement the hardware language code and algorithm for reconfiguration between two modes.

Student C Responsibilities

To apply different low power technologies in designing the target architecture and the approximate algorithm.

Student D Responsibilities

To develop design methodology for runtime reconfigurable FPGA.

Course Co-requisites

Digital Systems, knowledge of Computer Architecture, and FPGAs