10 Gbps Serial Data Links with Jitter Adaptive DFE and Phase-Track CDR

2019 ELE Engineering Design Project (FY02)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

High-speed serial data links are the backbone of cloud-centered applications. To combat the deterioration of signal integrity at high frequencies caused by the loss of wire channels, reflection at vias and connectors due to impedance mismatch, and crosstalk with neighboring devices at high frequencies, a number of channel equalization techniques have emerged. Among them, pre-emphasis and post-equalization are most effective. Channel equalization needs to be adaptive so as to compensate for the effect of the time-varying characteristics of channels. In addition to channel equalization, clock is transmitted with data as data transitions and needs to be recovered at the receiver. This capstone design project is concerned with the design of a 10 Gbps (giga-bits-per-second) serial data link.

Objective

Develop and implement a CMOS chipset (a transmitter and a receiver) for multi-Gb/s serial data communication over wire channels using a TSMC 65 nm CMOS technology.

Partial Specifications

1) Data rate: 10 Gbps.
2) Near-end pre-emphasis and far-end decision feedback equalization.
3) Clock and data recovery using phase-tracking.
4) Technology: TSMC 65 nm 1.2 V CMOS.
5) Silicon realization of the transmitter and receiver.

Suggested Approach

1) Study the fundamental of serial data communications over wire channels.
2) Develop the architecture of the system.
3) Develop the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Simulate the entire transceiver (schematic-level) to ensure that the design specifications are met.
6) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet the design specifications.
7) Conduct post-layout simulation of the entire design to ensure design specifications are met.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

Serializer, pre-emphasis block, driver, and transmitter frequency synthesizer that provides system clocks for the transmitter.

Student B Responsibilities

Continuous-time linear equalizer and jitter-based adaptive decision feedback equalizer.

Student C Responsibilities

Digitally controlled oscillator, phase-tracking clock and data recovery.

Student D Responsibilities

Synthesize the entire system using Verilog-A.

Course Co-requisites

ELE 863