All-Digital Delta-Sigma ADC with Oscillator-Based Time Integrator

2019 ELE Engineering Design Project (FY05)


Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

Analog-to-Digital Converters (ADCs) play an important role in many aspects of our daily life. Among various architectures of ADCs. Delta-sigma ADCs offer the highest resolution achieved via oversampling and noise-shaping. These ADCs are attractive for applications where signal bandwidth is small. The advance of CMOS technology has resulted in stiff difficulty in design of integrators in the forward path of delta-sigma ADCs arising from a shrinking voltage headroom. Technology scaling, on the other hand, has sharply improved the timing characteristics of digital circuits. Time-mode signal processing where information is represented by the time difference between the transition of digital signals offers a technology-friendly means to combat difficulties encountered in design of mixed analog-digital systems including delta-sigma ADCs. This capstone design project is concerned with the design of an all-digital delta-sigma ADC using a time-based approach.

Objective

This capstone design project is concerned with the design of an all-digital delta-sigma ADC using a time-based approach.

Partial Specifications

1) Bandwidth: a few MHz.
2) Second-order of delta-sigma modulator (MASH).
3) Oversampling ratio: 32.
4) SNDR: No less than 60 dB.
5) Technology: TSMC 65 nm CMOS.

Suggested Approach

1) Study the fundamental of ADCs and delta-sigma modulators.
2) Study the fundamental of time-based signal processing.
3) Develop the architecture of the system and the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks.
5) Conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
6) Carry out silicon implementation of the building blocks.
7) Conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
8) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

The student is responsible for an in-depth investigation of time integrators and the pros and cons of the time integrators. The comparison of the time integrators should be quantified using simulation results. In addition, the student is required to propose, develop, design, implement (layout), analyze, and characterize a low-voltage oscillator-based time integrator.

Student B Responsibilities

The student is responsible for an in-depth investigation of the methods that extract the time residue and the pros and cons of these methods. The comparison of these methods should be quantified using simulation results. In addition, the student is required to propose, develop, design, implement (layout), analyze, and characterize a low-voltage time residue extractor and the level-2 time-based delta-sigma modulator.

Student C Responsibilities

The student is responsible for an in-depth investigation of the digital filters for the second-order MASH. The student is required to propose, develop, design, implement (layout), analyze, and characterize a digital filter.

Student D Responsibilities

The student is responsible for modeling and analysis of the second-order MASH delta-sigma ADC using Verilog-A. The student is required to develop all Verilog-A code for the synthesis of the ADC.

Course Co-requisites

ELE724

 


FY05: All-Digital Delta-Sigma ADC with Oscillator-Based Time Integrator | Fei Yuan | Wednesday August 28th 2019 at 04:45 PM