Time-Based Noise-Shaping SAR ADC for Low-Power Applications

2019 ELE Engineering Design Project (FY07)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

Analog-to-Digital Converters (ADCs) play an important role in nearly every aspect of our life. Among various architectures of ADCs, successive approximation register (SAR) ADCs introduced in 1950s and debuted in CMOS in 1970s played a major role in advancing the state-of-the-art of ADCs since their inception. Although popular in telephony and instrumentation where data rate is typically low in the past, SAR ADCs have re-established themselves as the most promising ADC architecture inherently crafted for modern CMOS technologies with emerging applications from biomedical instruments where power consumption is of a great importance to high-speed data links where conversion rate is paramount, accredited to their compatibility with technology scaling. A key block of SAR ADCs is a digital-to-analog converter (DAC) typically realized using capacitor arrays. These DACs suffer from high dynamic power consumption and an excessive silicon area. Lowering unit capacitance, though effective in reducing power consumption and silicon area, is sharply confronted with a rising noise floor and deteriorating effect of clock feed-through and charge injection. Techniques such as 2-stage binary-weighted capacitor arrays, though effective in lowering silicon area and power consumption, suffer from performance degradation arising from the parasitic capacitances of scaling capacitors. SAR ADCs with low power consumption and a small silicon area are critically needed. This capstone design project develops and design a noise-shaping capacitor-less SAR ADC using a time-based approach.

Objective

This capstone design project develops and design a noise-shaping capacitor-less SAR ADC using a time-based approach.

Partial Specifications

1) Noise-shaping time-based SAR ADC.
2) Power consumption less than 1 micro watt.
3) Data rate: kS/s.
4) INL: No more than 0.5 LSB.
5) ENOB: No less than 8.
6) Technology: TSMC 65 nm.

Suggested Approach

1) Study the fundamental of ADCs, SAR ADCs, and noise-shaping SAR ADCs.
2) Study the fundamental of time-based signal processing.
3) Develop the architecture of the system and the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
6) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

The student is responsible for an in-depth investigation of sample-and-hold circuits and low-power time comparators and the pros and cons of these blocks. The comparison of these blocks should be quantified using simulation results. In addition, the student is required to propose, develop, design, implement (layout), analyze, and characterize a low-voltage sample-and-hold and a low-power time comparator.

Student B Responsibilities

The student is responsible for an in-depth investigation of successive approximation registers and the pros and cons of these SARs. The comparison of these methods should be quantified using simulation results. The student is also response for extracting the residue and noise-shaping block of the SAR ADC. In addition, the student is required to propose, develop, design, implement (layout), analyze, and characterize a low-power SAR.

Student C Responsibilities

The student is responsible for an in-depth investigation of the digital-to-time converter. The student is required to propose, develop, design, implement (layout), analyze, and characterize the digital-to-time converter.

Student D Responsibilities

The student is responsible for modeling and analysis of the SAR ADC using Verilog-A. The student is required to develop all Verilog-A code for the synthesis of the ADC.

Course Co-requisites

ELE724