SerDes Transceiver with Adaptive DFE and Phase-Picking CDR

2021 ELE Engineering Design Project (FY01)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

High-speed serial data links are the backbone of cloud-centered applications. To combat the deterioration of signal integrity at high frequencies caused by the finite bandwidth of wire channels, reflection at vias and connectors due to impedance mismatch, and crosstalk with neighboring devices at high frequencies, a number of channel equalization techniques have emerged. Among them, pre-emphasis and post-equalization are proven to be most effective. Channel equalization needs to be adaptive so as to combat the impact of the time-varying characteristics of channels in an adaptive manner. In addition to channel equalization, clock is transmitted as data transitions and needs to be recovered from equalized data at the receiver, along with the recovery of transmitted data (Clock and data recovery). T

Objective

Design a CMOS SerDes transceiver for serial data links

Partial Specifications

1) Data rate: 10 Gbps.
2) Near-end pre-emphasis and far-end decision feedback equalization.
3) Clock and data recovery using phase-picking also known as oversampling.
4) Technology: TSMC 65 nm 1.2 V CMOS.
5) Silicon realization of the transmitter and receiver.

Suggested Approach

1) Study the fundamental of serial data communications over wire channels.
2) Develop the architecture of the system.
3) Develop the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Simulate the entire transceiver (schematic-level) to ensure that the design specifications are met.
6) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet the design specifications.
7) Conduct post-layout simulation of the entire design to ensure design specifications are met.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

Serializer, pre-emphasis block, driver, and transmitter frequency synthesizer that provides system clocks for the transmitter.

Student B Responsibilities

Continuous-time linear equalizer and data-state adaptive decision feedback equalizer.

Student C Responsibilities

Digitally controlled oscillator, phase-picking-based clock-and-data recovery.

Student D Responsibilities

Frequency synthesizer that generates a 5 GHz clock. The frequency synthesizer is to be used by both the transmitter and receiver.

Course Co-requisites

(ELE724 or ELE734) and ELE 863

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.