Fei Yuan
Microelectronics
High-speed serial data links are the backbone of cloud-centered applications. To combat the deterioration of signal integrity at high frequencies caused by the finite bandwidth of wire channels, reflection at vias and connectors due to impedance mismatch, and crosstalk with neighboring devices at high frequencies, a number of channel equalization techniques have emerged. Among them, pre-emphasis and post-equalization are proven to be most effective. Channel equalization needs to be adaptive so as to combat the impact of the time-varying characteristics of channels in an adaptive manner. In addition to channel equalization, clock is transmitted as data transitions and needs to be recovered from equalized data at the receiver, along with the recovery of transmitted data (Clock and data recovery).
Design a SerDes transceiver for serial data links
1) Data rate: 10 Gbps.
2) Near-end pre-emphasis and far-end decision feedback equalization.
3) Clock and data recovery using phase-tracking.
4) Technology: TSMC 65 nm 1.2 V CMOS.
5) Silicon realization of the transmitter and receiver.
1) Study the fundamental of serial data communications over wire channels.
2) Develop the architecture of the system.
3) Develop the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Simulate the entire transceiver (schematic-level) to ensure that the design specifications are met.
6) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet the design specifications.
7) Conduct post-layout simulation of the entire design to ensure design specifications are met.
The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.
Serializer, pre-emphasis block, driver, and transmitter frequency synthesizer that provides system clocks for the transmitter.
Continuous-time linear equalizer and jitter-based adaptive decision feedback equalizer.
Digitally controlled oscillator, phase-tracking-based clock-and-data recovery.
Frequency synthesizer that generates a 5 GHz clock. The frequency synthesizer is to be used by both the transmitter and receiver.
(ELE724 or ELE734) and ELE 863
FY02: SerDes Transceiver with Adaptive DFE and Phase-Track CDR | Fei Yuan | Tuesday August 31st 2021 at 09:24 AM