Fei Yuan
Microelectronics
Analog-to-Digital Converters (ADCs) play an important role from biomedical sensors to cellular phones. Among various architectures of ADCs, successive approximation register (SAR) ADCs introduced in 1950s and debuted in CMOS in 1970s played a major role in advancing the state-of-the-art of ADCs since their inception. Although popular in telephony and instrumentation where data rate is typically low in the past, SAR ADCs have re-established themselves as the most promising ADC architecture inherently crafted for modern CMOS technologies with emerging applications in wireless sensors and biomedical instruments where power consumption is of a great importance The power consumption of SAR ADCs rises sharply with their resolution, mainly due to the increased transconductance of the front-end transistors of comparators needed to sense and amplify a very small voltage. As a result, the resolution of voltage-mode SAR ADCs is limited to approximately 10 bits. One attractive technique emerged recently is time-based comparators that are capable of detecting a very small input voltage without power-consuming voltage-mode comparators.
Design an 8-bit SAR ADC with a time-based comparator.
1) 8-bit differential SAR ADC with a time-based comparator.
2) Power consumption: a few micro watts.
3) Data rate: 10 kS/s.
4) INL (Integral nonlinearity): No more than 1 LSB.
5) ENOB (Effective number of bits): No less than 10.
6) Technology: TSMC 130 nm 1.2V CMOS.
1) Study the fundamental of ADCs and SAR ADCs.
2) Study the fundamental of time-based signal processing.
3) Develop the architecture of the system and the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
6) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.
The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.
The student is responsible for the design and implementation (schematic and layout) of the sample-and-hold (S/H) block of the SAR ADC. The performance of the S/H should be quantified using the spectrum of its output obtained using DFT analysis. The student is also responsible for the generation of the sampling clock that powers both the S/H and SAR using a frequency synthesizer that consists of a frequency detector, a charge pump, a voltage-controlled ring oscillator and a frequency divider.
The student is responsible the design and implementation (schematic and layout) of an 8-bit SAR, a differential capacitive DAC including the switching network, and SAR. The performance of the SAR ADC should be quantified using the spectrum of its output obtained using DFT analysis.
The student is responsible the design and implementation (schematic and layout) of the time-based comparator. The performance of the comparators such as input offset voltage should be quantified using Mote Carlo simulation. The performance of the time-based comparator should be compared with conventional strong-arm comparators in terms of power consumption, speed, and resolution so as to quantify its advantages and tradeoffs.
The student is responsible the design and implementation (schematic and layout) of the sampling clock that powers the S/H, SAR, and comparator. The sampling clock will be generated using a frequency synthesizer that locks to a reference clock. Student-4 should work closely with student-1 on the design of the frequency synthesizer.
ELE724 / ELE734 (at least two students should take ELE724)
FY05: SAR ADC for Low-Power Applications | Fei Yuan | Tuesday August 31st 2021 at 09:26 AM