Fei Yuan
Microelectronics
Analog-to-Digital Converters (ADCs) play an important role in from biomedical sensors to cellular phones. Among various architectures of ADCs, successive approximation register (SAR) ADCs introduced in 1950s and debuted in CMOS in 1970s played a major role in advancing the state-of-the-art of ADCs since their inception. Although popular in telephony and instrumentation where data rate is typically low in the past, SAR ADCs have re-established themselves as the most promising ADC architecture inherently crafted for modern CMOS technologies with emerging applications in wireless sensors and biomedical instruments where power consumption is of a great importance. The power consumption of SAR ADCs rises sharply with their resolution mainly due to the increased transconductance of the front-end transistors of comparators needed to sense and amplify a very small voltage. As a result, the resolution of voltage-mode SAR ADCs is limited to approximately 10 bits. One attractive technique emerged recently is the addition of noise-shaping capability to further digitize the residual voltage of the SAR ADC so as to achieve an improved resolution. These ADCs consist of a voltage-mode SAR ADC, a voltage-to-time converter (VTC) that maps the residual voltage of the SAR ADC to a time variable whose amplitude is proportional to that of the residual voltage, and a noise-shaping TDC (time-to-digital converter). One popular way to implement a noise-shaping TDC is to use a gated ring oscillator (GRO). The gating pulse of the GRO is the output of the VTC. The output of the GRO TDC is given by a counter that counts the number of cycles that the GRO performs and the logic state of the delay stages of the GRO.
Design a 8-bit-plus SAR ADC with GRO noise-shaping.
1) 8-bit voltage-mode SAR ADC with first-order noise-shaping delta-sigma modulation for resolution improvement.
2) Power consumption: a few micro watts.
3) Data rate: 10 kS/s.
4) INL (Integral nonlinearity): No more than 1 LSB (Least significant bit).
5) ENOB (Effective number of bits): No less than 8.
6) Technology: TSMC 130 nm 1.2V CMOS.
1) Study the fundamental of ADCs, SAR ADCs, VTC, and GRO.
2) Develop the architecture of the system and the specifications of the building blocks of the system.
3) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
4) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
5) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.
The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.
The student is responsible for the design and implementation (schematic and layout) of the sample-and-hold (S/H) block of the SAR ADC. The performance of the S/H should be quantified using the spectrum of its output obtained using DFT analysis. The student is also responsible for the generation of the sampling clocks that powers both the S/H and SAR. The sampling clock is generated using a frequency synthesizer that locks to a reference frequency.
The student is responsible the design and implementation (schematic and layout) of an 8-bit SAR, a differential capacitive DAC including the switching network, and comparator. The performance of the SAR ADC should be quantified using the spectrum of its output obtained using DFT analysis.
The student is responsible the design and implementation (schematic and layout) of the VTC. The performance of the modulator should be quantified using the spectrum of its output obtained using DFT analysis. The student is also responsible for the generation of the sampling clocks that powers both the S/H and SAR. The sampling clock is generated using a frequency synthesizer that locks to a reference frequency. Student-3 should also work closely with student-1 on the design of the frequency synthesizer that generates the required clocks.
The student is responsible the design and implementation (schematic and layout) of the GRO and its readout blocks. A counter that counts the number of the cycles that the GRO performs during the gating pulse also needs to be designed. In addition, a readout block that reads the transition of the logic state of the delay stages of the GRO needs to be designed.
ELE724 / ELE734 (at least two students should take ELE724)
FY06: SAR ADC with GRO-based Noise-Shaping for Low-Power Applications | Fei Yuan | Tuesday August 31st 2021 at 09:27 AM