Time approaches for mixed-mode signal processing
The advance of CMOS technology has always geared towards optimizing the performance of digital systems. As a result, CMOS analog circuits are continuously losing the benefits of specialized and process-controlled components critical to the performance of these circuits. In addition, they must also cope with a rapidly decreasing voltage headroom, i.e., the difference between the given supply voltage of a circuit and the minimum supply voltage of the circuit required for MOS transistors to operate in saturation, caused by the slow decline of the device threshold voltage and the aggressive reduction of the supply voltage while meeting ever stringent performance specifications. The shrinking voltage headroom not only limits the maximum achievable signal-to-noise ratio, it also signifies the effect of the nonlinear characteristics of MOS devices subsequently deteriorates the dynamic range of voltage-mode circuits. Further, technology scaling raises the thermal noise floor. As a result, the accuracy of voltage-mode circuits scales poorly with technology. The intrinsic gate delay of digital circuits, on the other hand, has been the primary beneficiary of technology scaling. The improved switching characteristics of MOS transistors offer an excellent timing accuracy such that the time resolution of digital circuits has well surpassed the voltage resolution of analog circuits implemented in nano-scale CMOS technologies. In a deep-submicron CMOS process, the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of an analog signal. Time-mode approaches where information is represented by the difference between the time instants at which digital events take place rather than the nodal voltages or branch currents of electric networks offer a new means to combat the scaling-induced challenges that once seemed unconquerable. Since time-mode circuits perform analog signal processing in the digital domain, not only the performance of these circuits scales well with technology, time-mode circuits also offer a number of attractive characteristics including full programmability, the ease of portability, low power consumption, and high-speed operation. This research project deals with the design, analysis, and verification of various time-mode building blocks for analog-to-digital data converters and all-digital phase-locked loops.
The RA will work closely with both Dr. Fei Yuan and his graduate students on the design, implementation, analysis, and verification of various time-mode building blocks for analog-to-digital data converters and all-digital phase-locked loops in an 65 nm CMOS technology.
The candidate must have completed ELE614 with a good grade. In addition, the candidate must also have achieved a good grade in ELE504.
Fei Yuan : Time approaches for mixed-mode signal processing | Monday February 27th 2017 12:06 PM