Implementation of Reconfigurable Classifier in FPGA

2019 Research Internship Project

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Faculty Name

Muhammad Jaseemuddin

Project Title

Implementation of Reconfigurable Classifier in FPGA

Project Description

Modern networks are designed to provide secure connectivity to a multitude of device for Internet of Things (IoT). The edge routers in such networks performs routing, NAT, deep packet filtering, firewall, intrusion detection (such as botnet) and caching etc. They are exceedingly used to provide wireless connectivity to mobile multimedia applications, monitoring and control of IoT devices, and support for service provider networks. They need flexibility of Software Defined Networking (SDN). Managing these devices and the network for achieving desirable objectives and optimal performance is an enormous task for average network user that needs to be developed with convenience of users in mind. Further, the management function should include monitoring, data collection, analysis, and create feedback control. In this project, a reconfigurable classifier will be designed and implemented for an SDN edge router. The SDN router with reconfigurable hardware provides modularity and flexibility as an edge device. The router interacts with a cloud-based IoT gateway that runs a dashboard is to collect the monitoring data from smart devices; analyse the data for measuring usage, monitoring failures and discovering trends; archive the data; present the data; and control device functions by generating control instructions with or without human intervention. The router includes a main processing component using off the shelf Linux board and an Intel DE1-SoC FPGA Accelerator Board. The Linux board implements the controller function running SDN Open Daylight controller. The controller function interacts with a Machine Learning based decision engine driven by data analytics collected from the IoT gateway dashboard. The Open Daylight SDN controller that will be augmented to interface with the FPGA board and reconfigure its logic. The DE1-SoC board is built using Altera SoC dual-core Cortex A-9 embedded ARM processor combined with FPGA logic integrated through high-speed interconnect. The FPGA board implements high-speed per-packet processing such as deep packet filtering, access control. The Cortex A-9 ARM processor implements a version of Ubuntu Linux. In this project a classifier will be designed and implemented for deep packet inspection and interaction with packet tracer.

Student Responsibility

1. Learn Intel DE1-SoC platform, install DE1-SoC system builder and test a demonstration Quartus II project. 2. Learn the SDN technology and Open Daylight controller especially its north-bound and south-bound API. 3. Read an example FPGA Quartus II project supplied in the manual to learn how a system is designed in FPGA. 4. Design a classifier for FPGA. 5. Implement the classifier in DE1-SoC and configure the FPGA. 6. Develop test cases and perform validation and performance testing. 7. Write a paper on the design and implementation of the classifier.

Specific Requirements

Students with background in C and VHDL programming and desire to learn systems development with FPGAs.