• ENG319
  • 416.979.5000 x554901
  • agye@torontomu.ca
  • Homepage

Courses

Andy Ye

Associate Professor

Andy Gean Ye received his Ph.D. degree in Computer Engineering from the University of Toronto in 2004. He also received his B.A.Sc. and M.A.Sc. degrees from the same university in 1996 and 1999, respectively. In 1996, he graduated first in class in the Engineering Science program; and from 1999 to 2000, he participated in the development of the Ultragizmo board for the University of Toronto Undergraduate Microprocessor Laboratory.

RESEARCH INTERESTS

Field-Programmable Gate Array (FPGA) architectures, Computer-Aided Design (CAD) tools for FPGAs, logic synthesis, and hardware implementation of computer graphics algorithms.

SELECTED PAPERS

  • PPing Chen and Andy Ye, "The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources," to appear in IEEE Transactions on Very Large Scale Integration Systems.
  • Andy Ye, "Using the Minimum Set of Input Combinations to Minimiz the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs," IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, No. 1, January 2010, pp. 95-107.
  • Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, We Mark Fang, and Jonathan Rose, "VPR 5.0: FPGA CAD and Architecture Exploration with Single-Driver Routing, Heterogeneity and Process Scaling," Proceedings of the 2009 ACM/SIGDA 17th International Symposium on Field-Programmable Gate Arrays, Monterey, California, February 2009, pp. 133-142.
  • Theepan Moorthy and Andy Ye, "A Scalable Computing and Memory Architecture for Variable Block Size Motion Estimation on Field-Programmable Gate Arrays," Proceedings of the 2008 IEEE 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, September 2008, pp. 83-88.
  • Phoebe Ping Chen and Andy Ye, "The Effect of Sparse Switch Patterns on the Area Efficiency of Multi-Bit Routing Resources in Field-Programmable Gate Arrays," Proceedings of the 2008 IEEE 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, September 2008, pp. 423-430.