RYERSON UNIVERSITY

Course Outline (W2019)

COE608: Computer Organization and Architecture

Instructor(s)Nagi Mekhiel [Coordinator]
Office: ENG446
Phone: (416) 979-5000 x 7251
Email: nmekhiel@ryerson.ca
Office Hours: Wed 12-1, Th 3-4
Calendar DescriptionThe main topics of the course include basic architecture of modern computers, interaction between computer hardware and software at various levels, and performance evaluation and metrics. Instruction set design, computer arithmetic is also discussed. Data path and control unit design for RISC Processors are covered in detail. The laboratory work includes the design and implementation of a 16-bit RISC CPU using an FPGA development system and VHDL.
PrerequisitesCOE 328 and COE 538 and CEN 199
Antirequisites

None

Corerequisites

None

Compulsory Text(s):
  1. Computer Organization and Design. The Hardware/ Software Interface, David Patterson and John Hennessy, 5 th edition 2013, Morgan Kaufmann Publishers, Elsevier Inc., ISBN 9780124078864

  2. Laboratory Manuals and other Documents: Available through the course web page:  http://www.ee.ryerson.ca/~courses/coe608/

Reference Text(s):
  1. Embedded Core Design with FPGAs, Z. Navabi, McGraw Hill 2007, ISBN 978-0- 07-147481- 8.

  2. Logic and Computer Design Fundamentals, Morris Mano & Charles R. Kime, 4th edition 2008 or latest edition, Prentice Hall.

Learning Objectives (Indicators)  

At the end of this course, the successful student will be able to:

  1. Interconnect engineering concepts related to instruction set architecture, register transfer, interconnects like buses, 3-state buffers and Muxes as well as control hardware to design various processors. Learn to employ specialized knowledge of subsystems like data-path, memory and control unit components to design a RISC processing element. (1c)
  2. Define processor specification and instruction set architecture. Solve various challenges of high performance RISC processor design in multiple stages by employing VHDL (CAD) based modeling and simulation methodologies to test and verify each stage of processor design and then integrate different stages into efficient processor architecture. (4b), (4c), (4a)
  3. Demonstrate the main features of all the labs and answer CPU design related questions during the demo/oral sessions. Write lab and CPU design reports by following a standard IEEE like format, where all the reports are evaluated based on their completeness, English, and relevant contents. (7a), (7b)

NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB).

Course Organization

3.0 hours of lecture per week for 13 weeks
2.0 hours of lab/tutorial per week for 12 weeks

Teaching AssistantsTBA
Course Evaluation
Midterm Exam 30 %
Labs with formal reports 30 %
Final Exam 40 %
TOTAL:100 %

Note: In order for a student to pass a course with "Theory and Laboratory" components, in addition to earning a minimum overall course mark of 50%, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section for details on the Theory and Laboratory components.


ExaminationsMidterm exam in Week 7 or 8, 1.5 hours, closed book (Weeks 1-7 lectures and labs).
 Final exam, during exam period, two hours, closed-book (covers Weeks 1-13 and labs).
Other Evaluation InformationThere will be bonus (optional) Lab-project component carrying additional 3-4% marks.
Other InformationNone

Course Content

Week

Hours

Chapters /
Section

Topic, description

1

3

Computer Systems Technology: Computer Organization VHDL


2

3

Instruction set Design:
  - Instruction representation.
  - Addressing modes.


3

3

Instruction set Design: Instructions for making decisions


4

3

Arithmetic for computers:
  - Integer arithmetic operations
  - Logical operations


5

3

Arithmetic for computers: ALU Design and Implementation


6

3

Computer Performance: Performance metrics and evaluation


7

3

Datapath: Register transfer and Interconnection Structures Data path Design


8

3

Datapath and Control: ASM Chart and Control Unit Design Single and Multi-cycle CPU Data-path Design


9

3

CPU Control Unit


10

3

CPU Control Unit Design and Implementation


11

3

Pipelining
  - Data Hazards
  - Stalls and Forwarding


12

3

Pipelining
  - Stalls and Forwarding
  - Branch hazards


13

3

Catching up and Review


Laboratory/Tutorials/Activity Schedule

Week

Lab

Description

2

ENG408

Lab1: Quartus-II FPGA Development Environment and Introduction to VHDL

3

ENG408

Lab 2: Program counter and Register set design: VHDL code Design and Simulation.

4

ENG408

Lab 3a: 32-bit ALU: VHDL design and simulation.

5

ENG408

Lab 3b: ALU Implementation on Altera Cyclone-IV and Testing

6

ENG408

Lab 4a: Data Memory Module Design and Implementation

7

ENG408

Lab 4b: CPU Datapath Design

8

ENG408

Lab 4b: CPU Datapath Design and Simulation

9

ENG408

Lab 4b: CPU Datapath Simulation and Submission
 Lab 5: CPU Control Unit Design

10

ENG408

Lab 5: CPU Control Unit Design

11

ENG408

Lab 5: CPU Control Unit – Submission
 Lab 6: Overall CPU Project - Integration and simulation of CPU.

12

ENG408

Lab 6: Integration and simulation of CPU. Fine-tuning and submission.
 Overall CPU Project Demonstration and Oral

13

ENG408

Overall CPU Project Bonus Demonstration and Oral

Policies & Important Information:

  1. Students are required to obtain and maintain a Ryerson e-mail account for timely communications between the instructor and the students;
  2. Any changes in the course outline, test dates, marking or evaluation will be discussed in class prior to being implemented;
  3. Assignments, projects, reports and other deadline-bound course assessment components handed in past the due date will receive a mark of ZERO, unless otherwise stated. Marking information will be made available at the time when such course assessment components are announced.
  4. Refer to our Departmental FAQ page for information on common questions and issues at the following link: https://www.ee.ryerson.ca/guides/Student.Academic.FAQ.html.

Missed Classes and/or Evaluations

When possible, students are required to inform their instructors of any situation which arises during the semester which may have an adverse effect upon their academic performance, and must request any consideration and accommodation according to the relevant policies as far in advance as possible. Failure to do so may jeopardize any academic appeals.

  1. Health certificates - If a student misses the deadline for submitting an assignment, or the date of an exam or other evaluation component for health reasons, they should notify their instructor as soon as possible, and submit a Ryerson Student Health Certificate AND an Academic Consideration Request form within 3 working days of the missed date. Both documents are available at https://www.ryerson.ca/senate/forms/medical.pdf.. If you are a full-time or part-time degree student, then you submit your forms to your own program department or school;
  2. Religious, Aboriginal and Spiritual observance - If a student needs accommodation because of religious, Aboriginal or spiritual observance, they must submit a Request for Accommodation of Student Religious, Aboriginal and Spiritual Observance AND an Academic Consideration Request form within the first 2 weeks of the class or, for a final examination, within 2 weeks of the posting of the examination schedule. If the requested absence occurs within the first 2 weeks of classes, or the dates are not known well in advance as they are linked to other conditions, these forms should be submitted with as much lead time as possible in advance of the absence. Both documents are available at www.ryerson.ca/senate/forms/relobservforminstr.pdf. If you are a full-time or part-time degree student, then you submit the forms to your own program department or school;
  3. Academic Accommodation Support - Before the first graded work is due, students registered with the Academic Accommodation Support office (AAS - www.ryerson.ca/studentlearningsupport/academic-accommodation-support) should provide their instructors with an Academic Accommodation letter that describes their academic accommodation plan.

Academic Integrity

Ryerson's Policy 60 (the Academic Integrity policy) applies to all students at the University. Forms of academic misconduct include plagiarism, cheating, supplying false information to the University, and other acts. The most common form of academic misconduct is plagiarism - a serious academic offence, with potentially severe penalties and other consequences. It is expected, therefore, that all examinations and work submitted for evaluation and course credit will be the product of each student's individual effort (or an authorized group of students). Submitting the same work for credit to more than one course, without instructor approval, can also be considered a form of plagiarism.

Suspicions of academic misconduct may be referred to the Academic Integrity Office (AIO). Students who are found to have committed academic misconduct will have a Disciplinary Notation (DN) placed on their academic record (not on their transcript) and will normally be assigned one or more of the following penalties:

  1. A grade reduction for the work, ranging up to an including a zero on the work (minimum penalty for graduate work is a zero on the work);
  2. A grade reduction in the course greater than a zero on the work. (Note that this penalty can only be applied to course components worth 10% or less, and any additional penalty cannot exceed 10% of the final course grade. Students must be given prior notice that such a penalty will be assigned (e.g. in the course outline or on the assignment handout);
  3. An F in the course;
  4. More serious penalties up to and including expulsion from the University.

The unauthorized use of intellectual property of others, including your professor, for distribution, sale, or profit is expressly prohibited, in accordance with Policy 60 (Sections 2.8 and 2.10). Intellectual property includes, but is not limited to:

  1. Slides
  2. Lecture notes
  3. Presentation materials used in and outside of class
  4. Lab manuals
  5. Course packs
  6. Exams

For more detailed information on these issues, please refer to the Academic Integrity policy(https://www.ryerson.ca/senate/policies/pol60.pdf) and to the Academic Integrity Office website (https://www.ryerson.ca/academicintegrity/).

Important Resources Available at Ryerson

  1. The Library (https://library.ryerson.ca/) provides research workshops and individual assistance. Inquire at the Reference Desk on the second floor of the library, or go to library.ryerson.ca/guides/workshops
  2. Student Learning Support(https://www.ryerson.ca/studentlearningsupport) offers group-based and individual help with writing, math, study skills and transition support, and other issues.