| Instructor(s) | Khalid Abdel Hafeez [Coordinator] Office: Online Phone: TBA Email: kabdelha@torontomu.ca Office Hours: Tuesday 10-11am | ||||||||||||
| Calendar Description | The main topics of the course include basic architecture of modern computers, interaction between computer hardware and software at various levels, and performance evaluation and metrics. Instruction set design, computer arithmetic is also discussed. Data path and control unit design for RISC Processors are covered in detail. The laboratory work includes the design and implementation of a 16-bit RISC CPU using an FPGA development system and VHDL. | ||||||||||||
| Prerequisites | CEN 199 and COE 328 and COE 538 | ||||||||||||
| Antirequisites | None | ||||||||||||
| Corerequisites | None | ||||||||||||
| Compulsory Text(s): |
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| Reference Text(s): |
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| Learning Objectives (Indicators) | At the end of this course, the successful student will be able to:
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB). | ||||||||||||
| Course Organization | 3.0 hours of lecture per week for 13 weeks | ||||||||||||
| Teaching Assistants | Daniel Segura(dsegura@torontomu.ca) Section 012, 032 Mahdiyar Ali Akbar Alavi (mahdiyar.alavi@torontomu.ca) Section 022, 042, 062, 082 Kevalkumar Shah (ttoor@torontomu.ca) Section 072, 092 Yasaman Ahmadiadli (yahmadiadli@torontomu.ca) Section 102, 122 Yasaman Ahmadiadli (ali.chitsazan@torontomu.ca) Section 052, 112 | ||||||||||||
| Course Evaluation |
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable). | ||||||||||||
| Examinations | Midterm exam will be in Week 7 or 8, 1.5 hours, closed book (Weeks 1-7 lectures and labs will be covered). Final exam will include all course materials. | ||||||||||||
| Other Evaluation Information | None | ||||||||||||
| Teaching Methods | lecture time Friday from 8-11am LIB072 Theater | ||||||||||||
| Other Information | None | ||||||||||||
Week | Hours | Chapters / | Topic, description |
|---|---|---|---|
1 | 3 | Introduction | |
2 | 3 | Computer Performance: Performance metrics and evaluation | |
3 | 3 | Instruction set Design: | |
4 | 3 | Instruction set Design: | |
5 | 3 | Input Output Systems | |
6 | 3 | Software: Assembler, Compiler, Linker, and Loader | |
7 | 3 | Datapath: | |
8 | 3 | Pipelining: | |
9 | 3 | Memory Hierarchy | |
10 | 3 | Memory and Cache System | |
11 | 3 | Arithmetic for computers: Integer arithmetic operations | |
12 | 3 | Arithmetic for computers: ALU Design and Implementation | |
13 | 3 | Catching up and Review |
Week | L/T/A | Description |
|---|---|---|
2 | ENG408 | Lab1: Quartus-II FPGA Development Environment and Introduction to VHDL |
3 | ENG408 | Lab 2: Program counter and Register set design: VHDL code Design and Simulation. |
4 | ENG408 | Lab 3a: 32-bit ALU: VHDL design and simulation. |
5 | ENG408 | Lab 3b: ALU Implementation on Altera Cyclone-IV and Testing |
6 | ENG408 | Lab 4a: Data Memory Module Design and Implementation |
7 | ENG408 | Lab 4b: CPU Datapath Design |
8 | ENG408 | Lab 4b: CPU Datapath Design and Simulation |
9 | ENG408 | Lab 4b: CPU Datapath Simulation and Submission |
10 | ENG408 | Lab 5: CPU Control Unit Design |
11 | ENG408 | Lab 5: CPU Control Unit - Submission |
12 | ENG408 | Lab 6: Integration and simulation of CPU. Fine-tuning and submission. |
13 | ENG408 | Overall CPU Project Bonus Demonstration and Oral |
Students are reminded that they are required to adhere to all relevant university policies found in their online course shell in D2L and/or on the Senate website
Refer to the Departmental FAQ page for furhter information on common questions.
You can submit an Academic Consideration Request when an extenuating circumstance has occurred that has significantly impacted your ability to fulfill an academic requirement. You may always visit the Senate website and select the blue radio button on the top right hand side entitled: Academic Consideration Request (ACR) to submit this request.
For Extenuating Circumstances, Policy 167: Academic Consideration allows for a once per semester ACR request without supporting documentation if the absence is less than 3 days in duration and is not for a final exam/final assessment. Absences more than 3 days in duration and those that involve a final exam/final assessment, require documentation. Students must notify their instructor once a request for academic consideration is submitted. See Senate Policy 167: Academic Consideration.
If a student is requesting accommodation due to a religious, Aboriginal and/or spiritual observance, they must submit their request via the online Academic Consideration Request (ACR) system within the first two weeks of the class or, for a final examination, within two weeks of the posting of the examination schedule. If the required absence occurs within the first two weeks of classes, or the dates are not known well in advance as they are linked to other conditions, these requests should be submitted with as much lead time as possible in advance of the required absence.
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Academic Accommodations (for students with disabilities) and Academic Consideration (for students faced with extenuating circumstances that can include short-term health issues) are governed by two different university policies. Learn more about Academic Accommodations versus Academic Consideration and how to access each.
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We encourage all Toronto Metropolitan University community members to access available resources to ensure support is reachable. You can find more resources available through the Toronto Metropolitan University Mental Health and Wellbeing website.