| Instructor(s) | Dr. Vadim Geurkov [Coordinator] Office: ENG430 Phone: (416) 979-5000 x 556088 Email: vgeurkov@torontomu.ca Office Hours: TBD | Calendar Description | The emphasis of this course is an understanding of the system architecture around the processor. Course covers all types of modern semiconductor memory, cache and virtual memory organization, hard disk drives and video-output subsystem. Course gives classification of buses and description of concepts of bus organization, bus protocols, arbitration mechanisms and the concept of Direct Memory Access (DMA). The laboratory projects include design of Cache Controller and VGA-signal generator using VHDL in Xilinx CAD environment. | ||||||||||||||
| Prerequisites | (COE 538 or ELE 538) and COE 608 | ||||||||||||||||
| Antirequisites | None | ||||||||||||||||
| Corerequisites | None | ||||||||||||||||
| Compulsory Text(s): |
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| Reference Text(s): |
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| Learning Objectives (Indicators) | At the end of this course, the successful student will be able to:
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB). | ||||||||||||||||
| Course Organization | 3.0 hours of lecture per week for 13 weeks | ||||||||||||||||
| Teaching Assistants | TBA | ||||||||||||||||
| Course Evaluation |
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable). | ||||||||||||||||
| Examinations | Midterm exam in Week 7, two hours, closed book, problem solving (covers Weeks 1-6). Final exam, three hours, closed-book, problem solving (covers all course material). | ||||||||||||||||
| Other Evaluation Information | The laboratory projects include design of IP-cores of custom on-chip modules for cache controller and video-signal generator for SVGA-monitor. Both projects include all major stages of on-chip design of custom digital systems: coding on VHDL hardware description language, compilation and design evaluation in Xilinx ISE CAD environment and hardware implementation on Xilinx Spartan FPGA platform. In assigned projects, students are required to develop the custom IP-cores on the basis of Xilinx Spartan FPGA development platform. The goal is to apply the theoretical knowledge to on-chip system design and get practical experience in VHDL-coding, simulation and on-chip verification of the designed module. There are two projects associated with different aspects of the system-on-chip (SoC) design: 1) IP-core design of the control-dominated circuit (Project 1: Cache Controller) and 2) IP-core design of the data-path dominated circuit (Project 2: Video-signal generator). For both projects the requirements are to demonstrate ability to create symbol of the system, develop system block-diagram, write the VHDL-code, compile and simulate it in Xilinx CAD environment, verify the behaviour on the Xilinx Spartan FPGA development platform using on-chip instrumentation (Chip-Scope), demonstrate the complete IP-core performance and submit the project report. Additionally, Project 2 requires integration the FPGA platform with the real-time I/O device (SVGA video-monitor) and demonstrate working project in all modes of operation. Lab Management The completed Tutorials account to 2% and lab Projects account for 14% each of the final mark. Each project must be demonstrated during the demonstration week. The project report must be submitted after successful project demonstration before the end of the demonstration week. The detailed evaluation of Lab components and projects is as follows: 1. 2% - Completed tutorials 2. 14% for each project: 2% - Symbol & block diagram design 3% - Compiled VHDL code demonstration 4% - Complete project demonstration on the FPGA platform 5% - Project report All the tutorials and projects could be done individually or in group of 2 students. Equipment should not be moved before, during or after the lab. In case if equipment seems to be defective it is a requirement to report to the lab instructor / technician who will take care of the problem. | ||||||||||||||||
| Teaching Methods | The teaching method is based on: a) presentation the theory component in in-person lectures using the white board and slides; b) recommended self-learning materials: text book chapters and lab tutorials and c) implementation of the theory in the associated lab projects to provide practical hands-on experience in system-on-chip (SoC) design and functional verification using a) on-chip verification tools (e.g. Xilinx Chip-Scope) and platform tools (e.g. Logic Analysers, video-monitors, etc.). | ||||||||||||||||
| Other Information | |||||||||||||||||
Week | Hours | Chapters / | Topic, description |
|---|---|---|---|
1 | 3 | B1: Ch.5/ 5.1 | 1. Introduction to COE 758: Scope and Objectives Management. |
2 | 3 | B1: Ch 5/ 5.2 | Types of electronic memory and their organization: |
3 | 3 | B1: Ch 5/ 5.3 | Cache memory organization: |
4 | 3 | B1: Ch 5/ 5.4 | Associative cache memory organization: |
5 | 3 | B1: Ch 5/ 5.7 | Virtual memory: concept and organization: |
6 | 3 | B1: Ch 5/ 5.7 | Virtual memory: concept and organization: |
7 | 2 | B1: Ch 5 / 5.1 - 5.8 | Midterm test: Preparation read: Book 1 Chapter 5 section 5.8 pp. 454-461 |
8 | 3 | B3 Ch 8 / 8.1-8.3 | Input-Output (I/O) subsystem organization: |
9 | 3 | B3 Ch 9 / 9.1-9.3 | Secondary data-storage devices: |
10 | 3 | B3 Ch 9 / 9.4 | Video-output subsystem organization: |
11 | 3 | B2 Ch 4 / 4.2 | Buses: 1. Classification of buses synchronization and handshaking |
12 | 3 | B2 Ch 4 / 4.2 | Bus arbitration and multi-level buses: |
13 | 2 | B3 Ch 8 / | Interaction between CPU I/O devices and memory: |
13 | 1 | Review and Catch-up |
Week | L/T/A | Description |
|---|---|---|
2 | Tutorial | Introduction to Xilinx ISE CAD and FPGA development environment |
3 | Project 1 Spec. | Tutorials: Design components in Xilinx Spartan FPGA. Project 1 Specification |
4 | Project 1 Symbol | Creation of the symbol and block diagram of the Cache Controller SoC |
5-6 | Project 1 VHDL | VHDL-coding and compilation. Creation of simulation/hardware emulation environment and verification |
7 | Project 1 Demo | Complete project 1 demonstration and report submission |
8 | Project 2 Spec. | Introduction to video-processing systems and Project 2 specification |
9 | Project 2 Symbol | Creation of the symbol and block diagram of the Video-Game Processor SoC |
10-11 | Project 2 VHDL | VHDL-coding and compilation. Creation of simulation environment and verification |
12 | Project 2 Demo | Complete project 2 demonstration and report submission |
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