Subject:
Code:
Level:
Venue:
Instructor:
Computer Organization and Architecture
COE 608
B.Eng. 3rd Year
Lecture:                    Lab: ENG408

  Electrical and Computer Engineering

COE 608: Computer Organization and Architecture
 

 
Announcements

  Course Outline

  Lecture Notes

  Labs

  Problem Sets

  FAQS

  Mid-Term Exam Sample

  Final Exam Sample

  Comment/ Feedback


 Welcome to  COE 608 Computer Organization and Architecture" website for Winter 2018. 
 

 Objective:

This course covers the basics of modern computer architectures. The emphasis is on understanding the interaction between computer hardware and software at various levels. The course covers the concepts of Computer technology, Performance Evaluation, Instruction set design, Computer arithmetic, Data path and Control unit design of processors and Enhancing performance with pipelining.

The laboratory work include the design and implementation of a RISC processor, using ALTERA FPGA development system, Quartus-II.

  Please contact your Instructor if you have any difficulties accessing this website. Some of the contents such as
   individual marks will be posted at the D2L Brightsight.
  • All notices and additional class materials will be posted time to time on this site.
  • The newest messages in the Announcements list are on top.
  • check this web site often, at least twice a week, to be sure that you don't miss anything.
  • It is your responsibility to keep up-to-date on the material contained at this website.
 Text Book
 David Patterson and John Hennessy, 
  "Computer Organization and Design. The Hardware / Software Interface" 
    4th or 5th edition, 2013 Morgan Kaufmann, Elsevier Inc.
    ISBN 978-0-12-374493-7, 978-0-12-407726-3

 Reference Text Book:
  M. Morris Mano and Charles R. Kime, 
  "Logic and Computer Design Fundamentals"  3rd or 4th edition
   Prentice-Hall, 2004, 2008. 


  LABS Venue: ENG408 

 Course Evaluation and Marking Scheme

  • Labs: 30%
  • Mid-Term Exam: 30%
  • Final Exam: 40%

 Please Note:
   1. There will be a 5% per day penalty for late submission of the labs and project
   2. All of the required course specific written reports including labs, projects and assignments will be assessed not only on
       their technical or academic merit, but also on the communication skills of the author as exhibited through these reports.
   
3. To achieve a passing grade in the course, the student must pass both the theory and laboratory/project components.
   4. Midterm exam will also cover the corresponding laboratories to enforce individual lab attempts.
   5. The students must follow and adhere to the senate policy 60 on Student Code of Academic Conduct.
       Available at:  http://www.ryerson.ca/senate/policies/pol60.pdf

                          This website will be updated continuously during the term