Subject:
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Instructor:
 Computer Organization and Architecture
COE 608
B.Eng. 3rd Year
Lecture:                    Lab: ENG408

  Electrical and Computer Engineering
COE 608: Computer Organization and Architecture


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 Lecture Notes

 Labs

 Problem Sets

 FAQS

 Mid-Term Exam Sample

 Final Exam Sample

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           Announcements for COE608: Computer Organization and Architecture  

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      4th Year Computer Engineering Course Selection Guidelines

    FINAL EXAM INFO and DETAILS   
Final Exam covers all the Lecture topics and Labs of the course.

MIPS CPU Data Sheet  is allowed in the exam if there is a machine code.

    4th Edition Problem Set-4  on Muti-Cycle Datapath/Control and Pipelining.
      Problem Set-4 
      4th Edition Problem Set-3  on CPU Single Cycle Datapath and Control Unit design.
      Problem Set-3 

       VHDL On-line Training and Tutorial    web-link posted
 1.  Introduction to Computer Organization   lecture notes
 2.  Introduction and  Review of VHDL lecture notes
 3.  Instruction Set Design and Architecture  lecture notes
             4th Edition Problem Set-1  ISA and Computer Arithmetics
 4.    Computer Performance   lecture notes
 5.    Register Transfer and Datapath   lecture notes
 6.    Single Cycle CPU Datapath   lecture notes
 7.    Single Cycle CPU Control   lecture notes
 8.    ASM based Control unit Design  lecture notes
 9.    Pipelining and Pipelined CPU Datapath-Control  lecture notes
 10.  Multicycle CPU Control  lecture notes  
 11.  Micrprogram  CPU Control Unit  lecture notes
 Lab-1 is posted : Quartus-II Tutorial
 Lab-2 is posted : CPU Register Set Design

 Lab-3a is posted : 32-bit ALU Design and Simulation
 Lab-3b is posted : 8-bit ALU Design Implementation and Testing
 Lab-4a is posted : Part-a:  Data Memory Module
 Lab-4b is posted :  CPU Data Path Design  
           CPU Specification for Lab-4, Lab-5
 Lab-5 is posted :  CPU Control Unit Design
 Lab-6 is posted :  CPU Integration and Testing
       MIPS CPU Data Sheet    
        The first lab session is scheduled in the 2nd week of Winter 2018 semester.           
       Summary of Course Management

  Course Evaluation and Marking Scheme
Labs: 30%
Mid-Term Exam: 30%
Final Exam: 40% 

        LABS Venue ENG408

  Please Note:
   I.    All the required course specific written reports including labs/assignments will be assessed not only on their
          technical/academic merit, but also on the communication skills of the author as exhibited through these reports.
   II.    To achieve a passing grade in the course, the student must pass both the theory and lab components.
   III.   There will be a 5% penalty per day for late submission of labs or project.
   IV.   The students must follow and adhere to the senate policy 60 on Student Code of Academic Conduct.
            Available at:  http://www.ryerson.ca/senate/policies/pol60.pdf