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                           TENTATIVE COURSE OUTLINE

WEEK                     LECTURE                                        LABORATORY 

  1     Computer Systems Technology: 
         Computer Organization, VHDL 

  2     Instruction set Design 
         Instruction representation,                      Lab1: Quartus-II-Altera FPGA Development Environment 
         Addressing modes                                             and introduction to VHDL, Lab Submission

  3     Instruction set Design                             Lab 2: Program counter and Register set design: 
         Instructions for making decisions                       VHDL code design and Simulation.

  4     Arithmetic for computers                        Lab 2: Submission
         Integer  Arithmetic Operations                Lab 3a: 32-bit ALU design
         Logical operations

  5      Arithmetic for computers                        Lab 3a: Submission  
          ALU Design and Implementation           Lab3b: 8-bit ALU Implementation                                 .

  6     Computer Performance                         Lab3b: Submission   
         Performance metrics and evaluation       Lab 4a: Data Memory Module      

  7     Register transfer                                       Lab 4a: Submission.
         Data path Design                                     Lab 4b: CPU Datapath design.

  8     Datapath and Control                            
         Single and Multi-cycle                           Lab 4b: CPU Datapath design and simulation
         Datapath Design         

  9    CPU Control Unit                                  Lab 4b: Submission
        ASM Charts and Control unit Design      Lab 5: CPU Control Unit design        

 10   Control Unit Design and                         Lab 5: Submission  
        Implementation                                       Lab 6: Integration of CPU

 11    Pipelining: Basic Concepts                     Lab 6: Integration and simulation of CPU 
                        
 12    Pipelining:                                               Lab 6: Submission
         Data Hazards,  Stalls and Forwarding      Bonus: CPU Project Demo & Submission

 13   Catching up and Course review