EE8501/ELE863 - VLSI Circuits for Data Communications
Dr. Fei Yuan
Department of Electrical and Computer Engineering
Toronto, Ontario, Canada
Tentative Course outline (click here)
- Modeling of wire channels
- Resistance, capacitance, and inductance of wire channels
- Lumped models of wire channels
- Distributed models of wire channels
- Transmission-line models of wire channels
- Electrical signaling
- Single-ended signaling
- Fully differential signaling
- Pseudo-differential signaling
- Low-voltage differential signaling (LVDS)
- Voltage-mode sigaling versus current-mode signaling
- Incremental signaling
- Fundamentals of serial links
- Pulse amplitude modulation (PAM)
- Pulse width modulation (PWM)
- Eye diagrams
- Inter-symbol interference (ISI)
- Bit-error rate
- Test of serial links
- Phase-locked loops (PLLs)
- Phase-frequency detectors
- Charge pumps
- Ring oscillators
- Stability of PLLs
- Phase noise of PLLs
- All-digital PLLs
- Channel equalization
- Bandwidth enhancement techniques
- Continuous-time linear equalization (CTLE)
- Decision feedback equalization (DFE)
- Adaptive DFE
- Clock and data recovery (CDR)
- Phase-picking CDR
- Phase-trackinhg CDR
- Instructor : Dr. Fei Yuan.
- Teaching Assistant : Matthew Dolan, Research Assistant.
No single text can serve as the text book of the course. Lecture notes will be provided
in lectures. Materials from the following reference books will also be used.
- W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
- K. Oh and X. Yuan (ed.), High-speed signaling : Jitter Modeling,
Analysis, and Budgeting, Prentice-Hall, 2012.
- H. Johnson and M. Graham, High-speed digital design - A handbook of
black magic, Prentice-Hall, 1993.
- F. Yuan, CMOS Current-Mode Circuits for Data Communications. Springer, 2006.
- F. Yuan (ed.), CMOS Time-Mode Circuits and Systems : Principles and Applications, CRC
- Stojanovic, Channel-limited high-speed links
: modeling, analysis and design, PhD Dissertation, Stanford University, 2004.
- Published peer-reviewed scientific papers in scientific journals and conference
- Laboratory project deals with the design of a complete data communication system consisting of a
transmitter, a wire channel, an adaptive decision feedback equalizer, and a clock and data recovery
- Laboratories will be running weekly during the scheduled laboratory time
slots. All laboratories must be conducted and completed individually.
- The laboratory report of each laboratory is due at the start of the next
- EE8501/ELE863 Laboratory Design
A set of assignments will be distributed over the term. Although these
assignments will not have a weight in the final grade of the course, it is
important for you to complete these assignments independently.
- Lab project : 30% (ELE 863)
- Lab project : 35% (EE 8501)
- Mid-term examination : 30% (ELE 863)
- Mid-term examination : 25% (EE 8501)
- Final examination : 40%
Lecture location & schedule
- Location : DSQ 05, Theatre.
- Sschedule : Thur. 9-12 am.
- Professor F. Yuan : Thur. : 3-4 pm, ENG 433.
- Matthew Dolan : TBD, ENG 402.