Picture of Dr.
                G. Khan
 Dr. Gul N. Khan 
Professor - Computer Engineering
Department of Electrical and Computer Engineering   
Ryerson University 350 Victoria St. Toronto, Ontario CANADA M5B 2K3 
Telephone: +(416) 979 5000 ext. 6084, Fax: +(416) 979 5280 
Email: gnkhan@ee.ryerson.ca   

Consultation Hours for Fall 2019 Semester: Monday 12:10-3:00PM (Office ENG 448)
4th Year Computer Engineering Course Selection Guidelines

Lecture Courses (Teaching Material):       
         COE718 Embedded System Design
         EE8205 Embedded Computer Systems 
         COE838 Systems-on-Chip Design

         COE608 Computer Organization and Architecture
         Real-time Operating Systems

Undergraduate Capstone Design Projects:
Design and FPGA-based Implementation of Cryptocurrency Mining Techniques
Design of an NoC based Multimedia System-on-Chip
Gate Reminder for a Smart Home
PCI-Express Interface Design and Implementation for ARM Cortex CPU 
CPU-GPU Implementation of Collision Detection for Gaming Applications
HDL Implementation of SATA I_O Protocol on a FPGA-based System
Hardware (RTL) Design of Secure Hash Functions for Crypto-currency Mining    
Design and FPGA Implementation of 2D-NoC based System-on-Chip
Authentication and Secure Data Exchange for Smart RF (Tag/Card) Systems

Current Research Interests: System-on-Chip, Network-on-Chip, NoC Synthesis and Design, Hardware/Software Codesign,  Real-time Embedded Systems, SoPC, Smart RFID Systems, Authentication Protocols, Fault Tolerant Software Systems, Intelligent System.
Research Student Supervision
Research Lab: Microsystems Research Lab    
PhD Candidates
to research in NoC Synthesis & Design, CPU-GPU Heterogeneous Computing, Hardware/Software Co-design, Network & System-on-Chip and RF Security Protocols are welcomed to apply for MASc/PhD Graduate admission at Ryerson Univ. In your admission application, mention me as your prospective supervisor.

Design and Research Projects:
         CAD tools for CPU-GPU systems and  CPU-GPU based Heterogeneous Computing.
         CAD tools for Network-on-Chip Synthesis and Design
         Design of an Efficient and High Performance NoC Router or NoC with minimal (optimal) latency, power and chip area.
         NoC Topology Generation and Analysis for High Performance MPSOCs
         Co-synthesis of Heterogeneous Multi-Task Embedded Systems with Real Time Constraints
         RFID-based Monitoring and Tracking of Elderly in a Smart Home

Associate Editor: Int. Journal Embedded and Real-Time Communication Systems
      Embedded and Networking Systems: Design, Software and Implementation , Eds. Gul Khan and Kris Iniewski,
    (CRC Press) Taylor & Francis, 2013

Recent and Selected Relevant Publications: See also Gul Khan at Google Scholar
   Application mapping to mesh NoCs using a Tabu-search based optimization, Microprocessors & Micro-systems, Vol. 55, 2017
  Efficient Dynamic Virtual Channel Organization and Architectures for NoC Systems , IEEE Trans. VLSI Systems, Vol 24, No. 2, February 2016
    Low Cost Authentication Protocol Scheme for Passive, Computational Capable RFID Tags,   Wireless  Networks, Vol. 21, No. 2, 2015
    Statically adaptive multi-FIFO buffer  Architecture for Network-on-Chip, Microprocessors & Microsystems, Vol. 39, No. 1, 2015
    High Performance NoC synthesis using analytical modelling and simulation,
Journal of Systems Architecture, Vol. 59, No. 7, 2013
    Secure Authentication Scheme for Passive C1G2 RFID Tags, Computer Networks Vol. 56, No. 1, 2012
   Designing Power and Performance Optimal Application-specific Network-on-Chip Architecture, Microprocessors & Microsystems, Vol. 35, No. 6, 2011
   A Modeling tool for Simulating & Design of On-chip Network Systems,   Microprocessors & Microsystems, Vol 34, No 3-4, 2010
   Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs, IEEE Trans. VLSI Systems, Vol 17, No. 4, 2009
   CAD tool for Hardware Software Co-synthesis of Heterogeneous Multiple Processor Embedded Architectures,  
                                                                                                                               Design Automation of Embedded Systems, Vol. 12, No. 4, 2008

   Adaptive and  Fault Tolerant Message Routing using DRB Approach
IEE/IET Proc. Computers & Digital Techniques, Vol. 127, No. 6,  2000
Advisory System for Colonoscopy , SPIE Proceedings 1999  
HPEC: Fault Tolerant Embedded System Architecture , Proceedings of ICCD, 1998

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