Picture of Dr.
                G. Khan
 Dr. Gul N. Khan 
Professor - Computer Engineering
Department of Electrical and Computer Engineering   
Ryerson University 350 Victoria St. Toronto, Ontario CANADA M5B 2K3 
Telephone: +(416) 979 5000 ext. 556084, Fax: +(416) 979 5280 
Email: gnkhan@ee.ryerson.ca   
 
Teaching
  Projects
  Experience
Publications
Citations
Research
List of Alumni
Education

Working on research projects related to GPU-based Heterogeneous Application Profiling and Auto-tuning.
Will be teaching COE718 & EE8205 courses in Fall 2021, and COE838/EE8221 in Winter 2022.

Consultation Hours: Online by appointment only (Office ENG 448)

Profile:
Dr. Gul N. Khan graduated in Electrical Engineering from UET, Lahore and completed his master’s in computer engineering from Syracuse University. After working as research associate at Arizona State University, he joined Imperial College of Science, Technology and Medicine, University of London and completed his Ph.D. He also worked as research associate for the Endoscope Automation project at Imperial College. Later on, Dr. Khan joined the computer systems engineering faculty of RMIT University, Melbourne. In 1997, Dr. Khan moved to Singapore and joined the computer system engineering faculty at Nanyang Technological University. Dr. Khan moved to Canada in 2000 and worked as Associate Professor of computer engineering at University of Saskatchewan before joining Ryerson University. He served as Program Director of Computer Engineering from 2004-2015. Dr. Khan has authored/edited a book entitled “Embedded and Networking Systems: Design, Software and Implementation” and he has published more than 125 refereed papers in journals, conference, symposium, and workshop proceedings as well as book chapters. Dr. Khan also hold three US patents. Currently, he is a Professor of Computer Engineering at Ryerson University. His research interests include Embedded Systems, CPU-GPU Systems, Heterogeneous Computing, Application Profiling and Tuning, HW-SW Co-design, NoC Design and SoC Synthesis.

Lecture Courses (Teaching Material):       
         COE718 Embedded System Design
         EE8205 Embedded Computer Systems 
         COE838 Systems-on-Chip Design

         COE608 Computer Organization and Architecture
         Real-time Operating Systems

Undergraduate Capstone Design Projects:
    Design and FPGA-based Implementation of Cryptocurrency Mining Techniques
    Design of an NoC based Multimedia System-on-Chip
    Gate Reminder for a Smart Home
    PCI-Express Interface Design and Implementation for ARM Cortex CPU 
    CPU-GPU Implementation of Collision Detection for Gaming Applications
    HDL Implementation of SATA I/O Protocol on a FPGA-based System
    Hardware (RTL) Design of Secure Hash Functions for Crypto-currency Mining    
    Design and FPGA Implementation of 2D-NoC based System-on-Chip
    Authentication and Secure Data Exchange for Smart RF (Tag/Card) Systems  

Current Research Interests: CPU-GPU Heterogeneous Systems, Auto-Tuning Tools for GPU-based Heterogeneous Systems, System-on-Chip, Network-on-Chip, NoC Synthesis and Design, Hardware/Software Codesign,  Real-time Embedded Systems, Intelligent System, Smart RFID Systems, Authentication Protocols.

Research Student Supervision:
Research Lab: Microsystems Research Lab    
PhD Candidates
to research in GPU-based Heterogeneous Computing, NoC Synthesis & Design, Hardware-Software Co-design and System-on-Chip are welcomed to apply for MASc/PhD Graduate admission at Ryerson Univ. I may not be able to respond to all the questions about graduate admission in our department. In your admission application, mention "Dr. Gul Khan" as your prospective supervisor and we will give due consideration to your admission application in our lab. See our selected List of Alumni

Design and Research Projects:
         CAD tools for CPU-GPU/GPGPU Systems and  CPU-GPU based Heterogeneous Computing.
         Profiling, Auto-Tuning and Application Partitioning for CPU-GPU Systems
         CAD tools for Network-on-Chip Synthesis and Design
.
         Design of an Efficient and High Performance NoC Router or NoC with Minimal (optimal) Latency, Power and Chip area.
         NoC Topology Generation and Analysis for High Performance MPSOCs
         Co-synthesis of Heterogeneous Multi-Task Embedded Systems with Real Time Constraints
 
Associate Editor:
1.
Int. Journal Embedded and Real-Time Communication Systems (IJRETCS)
2. Int. Journal of Reconfigurable and Embedded Systems (IJRES)

     Embedded and Networking Systems: Design, Software and Implementation , Eds. Gul Khan and Kris Iniewski, (CRC Press) Taylor & Francis, 2014

Recent and Selected Publications: See also Gul Khan at Google Scholar

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation, IET Circuits, Devices & Systems, 2021  download
Reconfigurable On-Chip Interconnection Networks for High Performance Embedded SoC Design,
Journal of Systems Architecture, Vol. 106, June 2020   download
Heterogeneous Design and Efficient CPU-GPU Implementation of Collision Detection, IADIS International Journal on Computer Science and Information Systems,
                                                                                                                                                                  Vol 14, No. 2, pp. 25-40, July-Dec
, 2019  download
Efficient and Low Power NoC Router Architecture, in High-Speed & Low Power Technologies: Electronics and Photonics, 2018 Taylor & Francis chap-9 download
Application Mapping to Mesh NoCs using a Tabu Search based Swarm Optimization, Microprocessors & Microsystems, Vol. 55, Nov. 2017   download 
Efficient Dynamic Virtual Channel Organization and Architectures for NoC Systems, IEEE Trans. VLSI Systems, Vol 24, No. 2, February 2016    download
Low Cost Authentication Protocol Scheme for Passive, Computational Capable RFID Tags,   Wireless  Networks, Vol. 21, No. 2, 2015   download
Statically adaptive multi-FIFO buffer  Architecture for Network-on-Chip, Microprocessors & Microsystems, Vol. 39, No. 1, 2015     download
High Performance NoC synthesis using analytical modelling and simulation, Journal of Systems Architecture, Vol. 59, No. 7, 2013     download
Secure Authentication Scheme for Passive C1G2 RFID Tags, Computer Networks Vol. 56, No. 1, 2012     download
Designing Power and Performance Optimal Application-specific Network-on-Chip Architecture, Microprocessors & Microsystems, Vol. 35, No. 6, 2011  download
A Modeling tool for Simulating & Design of On-chip Network Systems,   Microprocessors & Microsystems, Vol 34, No 3-4, 2010   download
Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs, IEEE Trans. VLSI Systems, Vol 17, No. 4, 2009   download
CAD tool for Hardware Software Co-synthesis of Heterogeneous Multiple Processor Embedded Architectures,      download

                                                                                                                                                             Design Automation of Embedded Systems, Vol. 12, No. 4, 2008
      Adaptive and  Fault Tolerant Message Routing using DRB Approach, IEE/IET Proc. Computers & Digital Techniques, Vol. 127, No. 6,  2000    download 
      Advisory System for Colonoscopy,  SPIE Proceedings 1999    download  
      HPEC: Fault Tolerant Embedded System Architecture, Proceedings of ICCD, 1998     download


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