NoC Topology Generation and Analysis for High Performance MPSOCs
This project intends to investigate new approaches to the design and analysis of NoC topologies, which is based on the transaction-oriented communication methods of on-chip components. Various algorithms are considered that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task. In addition, to aid the design process of complex systems, the design methodology should incorporate a form of predictive analysis, which can estimate the degree of contention in a given system without performing detailed simulation. Such predictive analysis method can also determine the minimum frequency of operation for generated topologies, and can be incorporated into the topology generation process. The proposed design method will be tested using real-word applications, including an MPEG4 decoder, Multi-Window Display and other application. The generated topologies must offer similar or better performance when compared with regular topologies. However, the topologies generated by new techniques should be more economical, using lower network resources as compared to regular topologies.