Nagi N. Mekhiel

  • Professor
  • Department of Electrical & Computer Engineering 
  • Ryerson University
  • Contact Information:

  • 245 Church St., Toronto, ON.
  • George Vari Engineering and Computing Centre, Office# 446
  • Tel: (416) 979-5000 Ext.7251
  • Email: nmekhiel@ee.ryerson.com
  • Research:

  • My research area is in computer architecture, parallel processing, and advanced memory systems. The research is focused in finding Novel solutions to processor/memory speed gap and the scalability of parallel computers to assure continuous improvement of performance.

    My research has been used and cited in many patents throughout the years by IBM, Google, Apple, Intel, Microsoft, Infineion, Micron, Canon, SUN Microsystems, Hitachi, and more.

     

  • Our Research has been awarded access to  an Intel Xeon+FPGA system via Intel's Hardware Accelerator Research Program.
  • Students:

  • I am currently accepting a M.A.Sc. student to work on the "Hardware Accelator" for Intel in conjuction with their Hardware Accelerator Research Program. Interested students may contact me by email. 

  • Biography:

    • Professor with the Department of Electrical and Computer Engineering (ECE), Ryerson University, Toronto, Ontario, Canada.
    • Inventor Collaborating with the Conversant Intellectual Property Management, Ottawa, ON, Canada
    • Inventor Collaborating with the Intellectual Ventures, Bellevue, WA, USA
    • Nagi N. Mekhiel received the B.SC.Electrical Engineering degree (Communication) in Electrical Engineering from Assiut University, Egypt in 1973, and the M.A.Sc. from University of Toronto in 1981 and Ph.D. degree in Computer Engineering from McMaster University, Hamilton, Ontario, Canada in in 1995.
    • He worked from 1981 to 1987 with the Hospital for Sick Children, Biomedical Research Institute, Toronto, Canada as a Biomedical Engineer, Designed microprocessor based systems for Chemotherapy, Antibiotic and Insulin infusion and licensed the System to Pancretec, a company in San Diego.
    • In 1987 he joined Definicon Systems Corporation, Newbury Park, California, USA as a Senior Hardware Engineer to 1990, Designed Computer systems using AMD, SPARC and Motorola Processors, Published many design ideas for high performance memory that have been used in many patents until today.
    • From 1996 to 1998, he worked with Yarc System Corporation Newbury Park, California, USA as a Senior Member of Technical Staff, Designed single and multiprocessor systems using Power-Pc for Image Processing.
    • In 1997 he worked at University of California Santa Barbara, Santa Barbara, California, USA as a Lecturer in the Department of Electrical and Computer Engineering, Taught Fundamentals of Logic Design and Computer Organization.
    • Dr. Mekhiel is a Senior Member of the IEEE.

     

    Courses:

    • coe328 Digital Systems (undergraduate)
    • coe608 Digital Systems Engineering ( fourt year undergraduate)
    • COE818 Advanced Computer Architecture (4th year elective)
    • ee8218 Parallel Computing (graduate)
    • ee8207High Performance Computer System Design (graduate)

     

     Selected Publications:

    • Nagi Mekhiel, "Hardware Accelerator for Serial Code Using Successive Forwarding for Multi-Core Processor", Accepted for Intel Collaboration Hub ISC17, June 19-21 2017, Frankfurt, Germany.
    • Nagi Mekhiel, “Parallel Vector Processing Using Multi Level Orbital Data”, International Journal of Computer, Electrical, Automation, Control and Information Engineering Vol:11, No:3, 2017 paper
    • Nagi Mekhiel, -Introducing TAM: "Time Based Access Memory”, IEEE Access journal, SPECIAL SECTION ON SECURITY AND RELIABILITY AWARE SYSTEM DESIGN FOR MOBILE COMPUTING DEVICES, March 30, 2016.P1061-1073 Volume 4. paper
    • Parallel Implementation of Image Matching with MPI,Alejandro Alfonso (Ryerson University, Canada) ,Ismail Sheikh (Ryerson University, Canada) ,Nagi Mekhiel (Ryerson University, Canada), IEEE CCECE 2016 Vancouver, Canada May15-18
    • Mekhiel, , “Cache Filter Method Based on DRAM Access Frequency to Improve System performance’’, HPSC 2015, NEW YORK, USA Aug23-26.
    • Mekhiel, “Multi-Level Processing to Reduce Cost of Synchronization’’, HPSC 2015, NEW YORK, USA Aug23-26.
    • Take the 'No Instruction' road past memory straits ''EE Times
    • Easily upgrade a 68030-based system with a clever cache design'' Electronic Design
    • DRAM control scheme speeds memory access,'' EDN
    • Oluwaseun Owojaiye, N. Mekhiel "Parallel Implementation of Non-Slicing Floorplan with MPI and OpenMP'', 27th International Conference on Computers and Their Applications, March12-14, 2012, Las Vegas USA
    • Gary Thorpe, N. Mekhiel "Modeling an Adaptive Memory Controller", Intl. Journal on Computers and Their Applications, December 2010.
    • Gary Thorpe, N. Mekhiel "DDR SDRAM Performance: Locality versus Parallelism", ISCA 20th INTERNATIONAL CONFERENCE ON COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING ,November 7-9, 2007, San Francisco, California, USA
    • Nagi Mekhiel, Analyzing Relationship between Technology and Job Skills, IT Skills in a Tough Job Market Symposium,Computer Science, California Lutheran University, Aug 02, 2006
    • Nagi Mekhiel, "Understanding The Behavior of Simultaneous Multithreaded, Multiprocessor and Multiprocessor with Simultaneous Multithreaded Architectures'', ISCA 21st International Conference on Computers and Their Applications (CATA-2006), March 23-25, 2006, Seattle, USA.
    • Zhen Yu, Nagi N. Mekhiel, "Comparison of Cache Simulation for Contemporary Simulators'', International Conference on Computer Science and its Applications (ICCSA-2003) July 01-02 , 2003, San Diego, California, USA.
    • Nagi Mekhiel, "LHA: Latency Hiding Algorithm for DRAM'' 2nd Annual Workshop on Memory Performance Issue (WMPI 2002). Held in conjunction with the ISCA 2002, May 25, 2002, Anchorage, Alaska. PAPER
    • Nagi Mekhiel, "The Effect of an Intercepting Cache on the Performance of Fast Page and Cache DRAM'' 13th International Conference on Computers and Their Applications, March 25-27, 1998, Honolulu, Hawaii. paper
    • Nagi Mekhiel, "Introducing SCSD `Shared Cache for Shared Data' Multiprocessor Architecture'', 10th International Conference on Parallel and Distributed Computing Systems, Oct.1-3, 1997, New Orleans, Louisiana, USA. PAPER
    • Nagi Mekhiel," Multi-Level Cache with Most Frequently Used Policy: A New Concept in Cache Design,'' ISCA International Conference on Computer Applications in Industry and Engineering, November 29 - December 1, 1995, Honolulu, Hawaii. PAPER
    • N. Mekhiel, "Evaluating the Design of a Three Level Cache System'', ISCA International Conference on Computer Application in Industry and Engineering, December 15-17, 1994, San Diego, California.
    • N. Mekhiel, "Performance Modeling of Hierarchical Memory Systems'', 1994 Canadian Conference on Electrical and Computer Engineering, September 25-28 1994, Halifax Canada.
    • N. Mekhiel, "Methods for improving main memory performance'', ISCA International Conference on Computer Applications in Industry and Engineering Honolulu, Hawaii, December 15-17, 1993.
    • N. Mekhiel, "Performance Analysis for a Cache System with Different DRAM Designs'', 1993 Canadian Conference on Electrical and Computer Engineering, Sep 14-17 1993, Vancouver Canada. paper
    • N. Mekhiel, "A Simple analytical model for a two level cache in a shared memory multiprocessor architecture'' Workshop on Portability and Performance for Parallel Processing, July 13-15,1993. Southampton, Hampshire, England.
    • N. Mekhiel, "Performance analysis of a two level cache system'', 26th Asilomar conference on Signals,Systems and Computers, October 26-28, 1992, Asilomar, California, USA.
    • T. Marshall, N. Mekhiel, W. Jackman, K. Perlman and M. Albisser, "Microprocessor based flow rate controller for Glycemic normalization with portable insulin delivery system,", Assisi, Italy,1981.

     

    Patents:

    • Mekhiel, "Bandwidth Amplification Method Using Interleaving of Latched Data and Multi Phase Clocking," licensed to Intellectual Ventures US and filed for patenting in 2016. patent
    • Mekhiel, "Reconfigurable ROW DRAM," licensed to Intellectual Ventures US and filed for patenting in 2016. patent
    • Mekhiel, "Cache Filtering Method and Apparatus", Patent US2010/0070709 B2, Jan 7, 2014 (patent).
    • Mekhiel, "Multi-Level Processing" Patent Application Nov 2010 (patent1 patent2).
    • Mekhiel, "DATA PROCESSING WITH TIME-BASED MEMORY ACCESS" US 2009/0113159 (patent1 patent2).
    • Mekhiel, "Methods And Apparatus For Accelerating Retrieval Of Data From A Memory System With Cache By Reducing Latency", Patent No: US 6,892,279 B2 May 10, 2005.
    • Mekhiel, "Methods and apparatus for reducing latency in a memory system", Patent No: US 6,587,920 B2 July 1, 2003.
    • Mekhiel, "Methods and apparatus for reducing latency in a memory system", Patent No: CA 2,327,134 Nov 30, 2000.
    • Mekhiel, "Methods and apparatus for reducing latency in a memory system", Patent No: EP 1998894.8 Nov 28, 2001.
    • Mekhiel, "Methods and apparatus for reducing latency in a memory system", Patent No: JP 2002-547003, Nov 28, 2001.
    • Mekhiel, "Method and apparatus for reducing latency in a memory system by interleaving SRAM and DRAM accesses", United States Patent 20030200408, 10/23/2003. (patent1 patent2 patent3 patent4 patent5 patent6)

     

    My Patents have been used in several industries: