B.Sc., M.Sc. Kassel, Ph.D. Hannover, P.Eng., SM-IEEE

2001- Present Professor, Toronto Metropolitan University, Department of Electrical and Computer Engineering
2000-01 Assistant Professor, Beheshti University, Tehran
1998-99 Nokia Research Center, Bochum, Germany
1996-99 Bosch Research Center, Stuttgart, Germany
1995-98 Research and Teaching, University of Hannover, Germany

Dr. Reza Sedaghat

Dr. Reza Sedaghat received his Ph.D. degree in Electrical Engineering from the University of Hannover, Germany. He joined the Department of Electrical and Computer Engineering at Toronto Metropolitan University, Toronto, Canada in 2001 and was promoted to Professor in 2012. He is the founder, director, and principal investigator (PI) of Optimization Problems Research and Applications Laboratory (OPRAL). OPR-AL was funded in 2003 from Sun Microsystems, Motorola, Canada Foundation for Innovation (CFI), Ontario Innovation Trust (OIT), Natural Sciences and Engineering Research Council of Canada (NSERC), and Toronto Metropolitan University. His industrial experience includes collaborations in Germany with Nokia Research Center, Robert Bosch GmbH, and Infineon Siemens as well as AMD and Blackberry in Canada. Dr. Sedaghat directs a research group working on radio resource management (RRM) security and radio access & networking (RAN) areas within OPR-AL. His current research interests include cryptanalysis on chip, cross layer design and optimization, attack immunity, combinatorial optimization problem, quadratic assignment problem, and graph algorithms. Dr. Sedaghat is currently serving as a reviewer for ACM Transactions on Design Automation of Electronic Systems, editor and reviewer for Journal of Microelectronics Reliability, Microelectronics Journal, and Science Direct Elsevier.

Optimization Problems Research and Applications Laboratory

OPR-AL is located in the heart of downtown Toronto, Canada. Our major focus is to investigate the theory, implementation, application and development of advanced Optimization approaches in Communication networking and security systems as well as VLSI systems. Our research topics include applied mathematics, the combinatorial optimization problem, the quadratic assignment problem, and graph algorithms, as well as the application of state-of-the-art technology in system synthesis.

4 Patents, 100+ Publications	70+ Graduate Alumni
Success stories with high ranking positions at IMAX, NVIDIA, Blackberry, AMD, Qualcomm, Siemens, Infineon,etc.
3 OPR-Lab graduated students are Professors	15+ Research Assistants

Research Projects

Communication Systems

Will be updated

VLSI

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Biomedical

OPR-AL has research interests in biomedical applications.

Publications

Patents

System and method for development of a system architecture Reza Sedaghat, et al., US Patent, United Sates Patent and Trademark Office (USPTO), US20120303560, Granted.
System and method for development of a system architecture Reza Sedaghat, et al., Canadian Patent Granted for Canadian Intellectual Property Office (CIPO) CA 2741253, Granted.
System and Methodology for Development of System Architecture Reza Sedaghat, et al., US Patent, United Sates Patent and Trademark Office (USPTO), US20120159119, US8397204, Granted.
System and Methodology for Development of System Architecture Reza Sedaghat, et al., Canadian Patent filed for Canadian Intellectual Property Office (CIPO), CA 2726091, Granted.

Journals

P. Siddavaatam, Reza Sedaghat, "A New Bio-heuristic Hybrid FekOO Algorithm for Continuous Optimization Problems", Transactions on Computational Collective Intelligence, TCCI, Springer, 2022, Accepted
P. Siddavaatam, Reza Sedaghat, N. Sahelgozin, "A Novel Machine Learning Framework for Covid-19 Image Classification with Bio-heuristic Optimization", Transactions on Computational Science,Springer, Vol. XXXIX, pp 85-108, 2023
Noel. Laiju , Reza Sedaghat, P. Siddavaatam, "Novel hybrid GWO-WOA and BAT-PSO Algorithms for solving design optimization problems", Transactions on Computational Science, Springer, Vol. XXXVIII, pp 113-144, 2021
P. Siddavaatam, Reza Sedaghat, "A New Bio-heuristic Hybrid Optimization for Constrained Continuous Problems", Transactions on Computational Science, Springer,XXXVI, pp 76-97, 2021
P. Siddavaatam, Reza Sedaghat, “A Novel Multi-Objective Optimizer Framework for TDMA-Based Medium Access Control in IoT”, Springer, CSI Transactions on ICT, Vol. 8, pp 319-330, 2020
P. Siddavaatam, Reza Sedaghat, “Grey Wolf Optimizer Driven Design Space Exploration: A Novel Framework for Multi-Objective Trade-off in Architectural Synthesis”, Elsevier Journal on Swarm and Evolutionary Computation, Volume 49, Pages 44-61, 2019
P. Siddavaatam, Reza Sedaghat, "A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers" Springer Journal of Hardware and Systems Security, Pages 1-19, 2019 .
P. Siddavaatam, Reza Sedaghat, "A Delta-Diagram based Synthesis for Cross layer Optimization Modeling of IoT", Springer Transactions on Computational Science XXXIII, pp. 1-24, 2018
P. Siddavaatam, Reza Sedaghat, "A Novel Architecture with Scalable Security Having Expandable Computational Complexity for Stream Ciphers", Journal of Facta Universitatis, Volume 30, No. 4, pp. 459 – 475, June 2017
Behnaz Abdoli, Reza Sedaghat, “Optimized Predictive Zonal Search (OPZS) for block-based motion estimation", Elsevier Jornal of Signal Processing: Image Communication, Volume 39, pp. 293–304, 2015.
Anirban Sengupta, Reza Sedaghat, “Swarm Intelligence Driven Design Space Exploration of Optimal k-Cycle Transient Fault Secured Datapath during High Level Synthesis Based on User Power-Delay Budget”, International Journal on Microelectronics Reliability, Elsevier, Volume 55, Issue 6, pp. 990–1004, 2015
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar “Rapid Exploration of Integrated Scheduling and Module Selection in High Level Synthesis for Application Specific Processor Design”, ‘Microprocessors and Microsystems Journal, Elsevier, Volume 36, Issue 4, pp. 303–314, 2012
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, “A Multi Structure Genetic Algorithm for Integrated Design Space Exploration of Scheduling and Allocation in High Level Synthesis for DSP Kernels”, Elsevier, Journal of Swarm and Evolutionary Computation, Volume 7, pp. 35–46, 2012
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, “Rapid Design Space Exploration by Hybrid Fuzzy Search Approach for Optimal Architecture determination of Multi Objective Computing Systems”, International Journal on Microelectronics Reliability, Elsevier, Volume 51, Issue 2, pp. 502-512, 2011
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, “Multi objective Efficient Design Space Exploration and Architectural Synthesis of an Application Specific Processor (ASP)”, Microprocessors and Microsystems Journal, Elsevier, Volume 35, Issue 4, June 2011, pp. 392-404
Reza Sedaghat, Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe “Switch-Level Emulation of Strength-Base Soft Error Detection” International Journal of Microelectronics Reliability Elsevier, Volume 51, Issue 3, March 2011, Pages 692-702, 2011
Anirban Sengupta, Reza Sedaghat, “A High Level Synthesis Design Flow from ESL to RTL with multi parametric optimization objective”, IETE Journal of Research, Volume 57, Issue 2, 2011, pp. 169-186.
Reza Javaheri, Reza Sedaghat, “Strength Violation Effect on Soft-Error Detection in Sub-micron Technology” International Journal of Microelectronics Reliability, Science Direct, Elsevier, Volume 50, Issue 7, pp 971-977, 2010
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, “A High Level Synthesis design flow with a novel approach for Efficient Design Space Exploration in case of multi parametric optimization objective”, International Journal of Microelectronics Reliability, Science Direct, Elsevier, Volume 50, Issue 3, , pp. 424-437, 2010
Reza Sedaghat, Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe "Switch-level soft error emulation for SET-induced pulses of variable strengths" Microelectronics Journal Elsevier, Volume 41, Issue 10, pp. 651-661, 2010
Reza Sedaghat, R. Javaheri, "Multi-valued Logic Mapping of Resistive Short and Open Delay Fault Testing in Deep Sub-Micron Technologies", International Journal of Microelectronics Reliability, Science Direct, Elsevier, Volume 49, Issue 2, 2009, Pages 178–185
P. Lee, Reza Sedaghat, "FPGA-based Switch-level Fault Emulation using Module-based Dynamic Partial Reconfiguration", International Journal of Microelectronics Reliability, Science Direct, Elsevier, Volume 48, Issue 10, 2008, Pages 1724-1733
M. Kunchwar, Reza Sedaghat, V. Geurkov, “Dynamic Behavior of Resistive Faults in Nanometer Technology”, International Journal of Microelectronics Reliability, Science Direct, Elsevier,Volume 47, Issue 12, 2007, pp. 2141-2146
Reza Sedaghat, M. Kunchwar, R. Abedi, R. Javaheri, “Transistor-level to Gate-level Comprehensive Fault Synthesis for n Input Primitive Gates”, International Journal of Microelectronics Reliability, Science Direct, Elsevier, Volume 46, Issue 12, December 2006, Pages 2149-2158
R. Javaheri, Reza Sedaghat, Leo Kant, Jason Zalev, “Verification and Fault Synthesis Algorithm at Switch-Level”, Journal of Microprocessors and Microsystems, Science Direct, Elsevier, Volume 30, Issue 4, 6 June 2006, pp 199- 208
H. Moon, Reza Sedaghat, “FPGA-based Adaptive Digital Predistortion System for Radio overâ€‘Fiber Links”, International Journal of Microprocessors and Microsystems, Science Direct, Elsevier, Vol 30/3, 2006, pp 145-154
J. Zalev, Reza Sedaghat, "Complex Energy Signal Model for Digital Human Fingerprint Matching", Transactions on Engineering, Computing and Technology, Enformatika Volume 13, ISSN 1305-5313, May 2006, pp 136-140
Reza Sedaghat, "Routability Estimation of FPGA-based Fault Injection", IEE Electronic Letter Journal, Vol. 41, Nr. 14, 07/2005, p. 790-793

Conferences

P. Siddavaatam, Reza Sedaghat and A. T. Sharma, “A Novel Multi-Objective Optimization Approach for Design Flow in High Level Synthesis”, IEEE 5th International Conference on Electrical, Electronics, Computers, Communication, Mechanical and Computing (EECCMC), pp. 192-204, 2018
P. Siddavaatam, Reza Sedaghat and N. Giamblanco, "Keyword and Keyphrase Extraction using Newton's Law of Universal Gravitation," IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1-4, 2017
P. Siddavaatam, Reza Sedaghat and A. T. Sharma, “intel-LEACH: An Optimal Framework for Node Selection using Dynamic Clustering for Wireless Sensor Networks”, IEEE 12th International Conference for Internet Technology and Secured Transactions (ICITST), Cambridge, pp. 159-167, 2017
M. H. Cheng, Reza Sedaghat, and P. Siddavaatam, “A New Adaptable Construction of Modulo Addition with Scalable Security for Stream Ciphers”, Network and System Security. NSS. Lecture Notes in Computer Science, vol 9955. Springer, pp. 383-397, 2016
Reza Sedaghat, Prathap Siddavaatam Min Hsuan Cheng, "An Adaptive Security Framework with Extensible Computational Complexityfor Cipher Systems", The 11th IEEE International Conference for Internet Technology and Secured Transactions (ICITST), pp: 133-139, 2016
Anirban Sengupta, Reza Sedaghat, “Priority Function Driven Design Space Exploration in High Level Synthesis Based on Power Gradient Technique”, 17th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2012), pp: 25, 2012.
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta, “Power Gradient Based Design Space Exploration in High Level Synthesis for DSP Kernels”, Proceedings of 23rd IEEE International Conference on Microelectronics (ICM), pp:1-6, Jan. 2012
Anirban Sengupta, Reza Sedaghat, “Integrated Scheduling, Allocation and Binding in High Level Synthesis using Multi Structure Genetic Algorithm based Design Space Exploration System”, Accepted for Publication in Proceedings of 12^th IEEE/ACM International Symposium on Quality Electronic Design (ISQED 2011), pp. 486-494, 2011
Anirban Sengupta, Reza Sedaghat, “A Hybrid Fuzzy Search Approach for Fast Design Space Exploration of Multi-Objective VLSI Systems”, Accepted for Poster in the Student Forum of 16th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, “Integrated design space exploration based on power-performance trade-off using genetic algorithm”, ACM Proceeding ACAI '11 Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011, pp. 77-81
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, “Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis”, ACM Proceeding ACAI '11 Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011, pp. 82-85
Anirban Sengupta, Reza Sedaghat, “Fast Design Space Exploration for Multi Parametric Optimized VLSI and SoC Designs”, 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, “Rapid Design Space Exploration for multi parametric optimization of VLSI designs”, IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 3164-3167
Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, “A Framework for Fast Design Space Exploration using Fuzzy search for VLSI Computing Architectures”, IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 3176-3179
Anirban Sengupta, Reza Sedaghat, “Rapid Exploration of Power-Delay Tradeoffs using Hybrid Priority Factor and Fuzzy Search”, In Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 355-358, 2010
Anirban Sengupta, Reza Sedaghat, “Accelerated Exploration of Cost-Performance Tradeoffs for Multi Objective VLSI designs”, In Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 100-103, 2010
Summit Sehgal, Reza Sedaghat, Anirban Sengupta, “Automated Design Space Exploration for DSP Applications High Level Synthesis with Stability in Competition”, Proceedings of 2nd IEEE Latin American Symposium on Circuits and Systems (LASCAS), In Press, 2011
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, “Integrated Scheduling, Allocation and Binding in High Level Synthesis for Performance-Area Tradeoff of Digital Media Applications”, In Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011), in Press, 2011.
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, “Priority Function based Power Efficient Rapid Design Space Exploration of Scheduling and Module Selection in High Level Synthesis”, In Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011), in Press, 2011.
Summit Sehgal, Reza Sedaghat, Anirban Sengupta, Zhipeng Zeng, “Multi Parametric Optimized Architectural Synthesis of an Application Specific Processor”, IEEE 14^th International CSI Computer Conference (CSICC), 2009, pp 89-94
R. Javaheri, Reza Sedaghat, "Dynamic strength scaling for delay fault propagation in nanometer technologies", IEEE 14^th International CSI Computer Conference (CSICC), pp 95-99, 2009
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, “Hardware Efficient Design of speed optimized Power stringent Application Specific Processor”, IEEE 21^st International Conference on Microelectronics (ICM), pp 167-170, 2009
Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, “A Novel Framework of Optimizing Modular Computing Architecture for multi objective VLSI designs”, IEEE 21^st International Conference on Microelectronics (ICM), pp 322-325, 2009
P.K.Kalkat, Reza Sedaghat, J.M.Chikhe, R.Javaheri "Soft error injection using advanced switch-level models for combinational logic in nanometer technologies”, IEEE 21st International Conference on Microelectronics (ICM), Published in the 21st Conference Proceedings, pp 326-329, 2009
R. Javaheri, Reza Sedaghat, "Multi-valued voltage model for Delay Fault Testing of Resistive Faults in Deep Sub-Micron Technologies", Springer Verlag, International CSI Computer Conference, CSICC, pp. 177-182, 2008
V. Geurkov, V. Dynkin, Reza Sedaghat, "An error-locating signature analyzer to identify faulty units in digital systems", IEEE VLSI Test Symposium, pp. 1073-1076, 2008
H. Moon, Reza Sedaghat, “Radio-over-Fiber Link Linearization using Adaptive Digital Predistortion”, Proc. Proc. IEEE International Symposium on Circuits and Systems, ISCAS, Accepted, 2006
H. Moon, Reza Sedaghat, “Design of Adaptive Digital Predistorter for Increasing Dyamic Range in ROF Link”, Proc. of the International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC, 2005
M.A. Zeinali, Reza Sedaghat, "Layout design of a 2D-LFSR for the E1/E2 multiplexer”, Proc. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 173-176, 2005
J. Zalev, Reza Sedaghat, "Automatic Fingerprint Recognition Algorithm", Proc. Canadian Conference on Electrical and Computer Engineering, CCECE, 2004
M.A. Zeinali, Reza Sedaghat, "Layout design of a 2D-BIST structure for the E1/E2 multiplexer", Proc. Canadian Conference on Electrical and Computer Engineering, CCECE, 2004
M.A. Zeinali, Reza Sedaghat, "Layout design of a 2D-CCLFSR structure", Proc. International Conference for Upcoming Engineers, ICUE, 2004
J. Zalev, Reza Sedaghat, " Preprocessing and Extracting Minutiae for Fingerprint Recognition Algorithm", Proc. International Conference for Upcoming Engineers, ICUE, 2004
T. Moon, Reza Sedaghat, "Adaptive Predistortion Techniques for Non-linear Components", Proc. International Conference for Upcoming Engineers, ICUE, 2004
Reza Sedaghat, “A Fast Algorithm to Reduce 2-Dimensional Assignment Problems to 1-Dimensional Assignment Problems for FPGA-based Fault Simulation”, Proc. IEEE International Symposium on Circuits and Systems ISCAS, pp. 102-105, 2003
Reza Sedaghat, P. Goravanchi, O. Hashemipour, "9th order linear phase baseband filter”, Proc. IEEE International Conference on Electronics, Circuits and Systems ICECS, accepted, 2003
S. Nadarajah, X. Fernando, Reza Sedaghat, “Adaptive Digital Predistortion of Laser Diode Nonlinearity for Wireless Applications”, Proc. Canadian Conference on Electrical and Computer Engineering CCECE, 2003
Reza Sedaghat, P. Goravanchi, O. Hashemipour, “A very low voltage 9^th order linear phase baseband switched capacitor filter”, Proc. Canadian Conference on Electrical and Computer Engineering CCECE, 2003
Reza Sedaghat, C. Lim, “Implementation of Regenerator Section Overhead (RSPH) for an SDH Chip”, Proc. International Conference for Upcoming Engineers, ICUE, 2003
Reza Sedaghat, B. O’Brien, “ ASIC Implementation of a Pseudo-random Test Pattern Generator Using a 32-bit Linear Feedback Shift Register (LFSR)”, Proc. International Conference for Upcoming Engineers, ICUE, 2003
Reza Sedaghat, E. Barke, “Real Time Fault Injection Using Logic Emulators”, Proc. Asia and South Pacific Design Automation Conference ASP-DAC’98, pp.475-479, 1998
Reza Sedaghat, “Fault Emulation with Optimized Assignment of Circuit Node to Fault Injectors”, Proc. IEEE International Symposium on Circuits and Systems ISCAS’98, pp.135-138, 1998
Reza Sedaghat, “Eine neue Methode zur Fehleremulation”, Proc. ITG-Workshop of Microelectronic and Information Technology, pp.77-81, 1998
Reza Sedaghat, E. Barke, “A New Approach to Fault Emulation”, Proc. 8^th IEEE International Workshop of Rapid System Prototyping RSP’97, pp.173-179, 1997
Reza Sedaghat, “Fehleremulation mit Logikemulationssystem”, Proc. 4^th SICAN-Workshop of Microelectronics and Microsystems, pp. 221-225, 1997

Others

Reza Sedaghat, J. Stohmann, Redesigned and evaluated DVB-T (Digital Video Broadcast-Terrestrial) receiver chip for FPGA-based emulation systems, Nokia-Research Report, No. Ba 324, 1999
Reza Sedaghat, PhD, Dissertation, Fault Emulation: Reconfigurable Hardware-Based Fault Simulation Using Logic Emulation Systems with Optimized Mapping, 1999
Reza Sedaghat, DFG-Research Report, Report period: 15.3.1995-15.3.1997, No. Ba 812/3-1, 1997
Reza Sedaghat, DEG-Research Report, Report period: 15.3. 1997-15.3.1998, No: Ba 812/3-2, 1998

Current Members

Patrick Siddavataam

Dr. Patrick Siddavataam is working at NXM Labs Inc. as a Research Scientist in the R&D area of applying Quantum Computing, Quantum Cryptography for 5G communications for IoT devices. His research works involves collaboration with IBM, ARM, Microsoft, Xanadu, and Sprint for implementation of quantum resistant and crypto agility technologies. He is also working as Post Doctoral Fellow (PDF) in the OPR Laboratory, Department of Electrical and Computer Engineering, Toronto Metropolitan University, Toronto, Canada. He also works as a lecturer in Department of Electrical and Computer Engineering, Toronto Metropolitan University, Toronto, Canada. He has worked in various capacities as a Systems developer for designing multi-domain products in different divisions of Microsoft Corporation, Robert Bosch GmbH and Siemens AG. His research interests include secure algorithms, security patterns, cryptography and building secure and optimized VLSI architectures.

Nahid Sahelgozin

Nahid is a MASc graduate student at OPR-AL focused on developing solutions for image processing theories. She is coordinating a research group developing image processing tools. Additionally, she is interested in field of Digital systems and Advanced Mathematics. Nahid is the Recipient of L'Ecole Polytechnique Award. Her current projects in OPR-AL is the development of Bio-heuristic Hybrid machine learning optimization.

Michael Sinclair

Michael is a MASc graduate student at OPR-AL. His background is originally in physics, having obtained a B.Sc Honours in Physics from Brock University. He is a Dean’s List student completed the B.Eng focused in Computer Engineering at Toronto Metropolitan University. He worked at Advanced Micro Devices (AMD) on mixed signal custom design chip, developing the physical layout of their products with a focus in high speed and high power clock circuitry. His current projects in OPR-AL is the development of mathematical modeling and optimization of machine learning for modulation of neural network systems.

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Supervised Students

Name

Jason Chang (Canada), nVIDIA
Charles Lim (Canada), eSight Eyewear
Reza Javaheri (Canada), Qualcomm
M. Kunchwar (Canada), Blackberry
P. Lee (Canada), AMD
Behnaz Abdoli (Canada), TYCO
A. Sengupta (Canada), Indian Institute of Technology, IIT, India
B. Abedi (Canada), BN University of Technology, Iran
W. Hartong (Germany), Siemens
R. Lee (Germany), Infineon
J. Zalev (Canada)
Zhipeng Zeng (Canada)
H. Moon (Canada)
L. Kant (Canada)
M. Torshizi (Canada)
A. Zeinali (Iran)
A. Morrison (Canada)
Jasmina Vasiljevic (Canada)
P. Hac (Canada)
A. Azad (Canada)
K. Adekunle (Canada)
S. Naderi (Canada)
S. Kilinc(Canada)
A. Abbas (Canada)
R. Leung (Canada)
D. Cerullo (Canada)
B. O'Brien (Canada)
T. Fung (Canada)

OPR-AL

Research & Innovation Centre